1
1
CONTENTS
CHAPTER 1 SOCKIT DEVELOPMENT KIT ..................................................................................................... 3
1.1 PACKAGE CONTENTS ................................................................................................................................................... 3
1.2
SOCKIT SYSTEM CD .................................................................................................................................................. 4
1.3
GETTING HELP ............................................................................................................................................................ 4
CHAPTER 2 INTRODUCTION OF THE SOCKIT BOARD................................................................................ 5
2.1 LAYOUT AND COMPONENTS ........................................................................................................................................ 5
2.2
BLOCK DIAGRAM OF THE SOCKIT BOARD .................................................................................................................. 8
CHAPTER 3 USING THE SOCKIT BOARD ................................................................................................... 10
3.1 BOARD SETUP COMPONENTS .................................................................................................................................... 10
3.1.1
JTAG CHAIN AND SETUP SWITCHES ...................................................................................................................... 10
3.1.2
FPGA CONFIGURATION MODE SWITCH ................................................................................................................. 12
3.1.3
HPS BOOTSEL AND CLKSEL SETTING HEADERS ............................................................................................... 13
3.1.4
HSMC VCCIO VOLTAGE LEVEL SETTING HEADER ............................................................................................... 15
3.2
BOARD STATUS ELEMENTS ....................................................................................................................................... 15
3.3
BOARD RESET ELEMENTS ......................................................................................................................................... 16
3.4
PROGRAMMING THE QUAD-SERIAL CONFIGURATION DEVICE ................................................................................... 17
3.5
CLOCK CIRCUITS ...................................................................................................................................................... 18
3.6
INTERFACE ON FPGA ................................................................................................................................................ 19
3.6.1
USER PUSH-BUTTONS, SWITCHES AND LED ON FPGA .......................................................................................... 19
3.6.2
HSMC CONNECTOR ............................................................................................................................................... 22
3.6.3
AUDIO CODEC ..................................................................................................................................................... 26
3.6.4
VGA ...................................................................................................................................................................... 27
3.6.5
IR RECEIVER .......................................................................................................................................................... 30
3.6.6
DDR3 MEMORY ON FPGA .................................................................................................................................... 30
3.6.7
TEMPERATURE SENSOR .......................................................................................................................................... 33
3.7
INTERFACE ON HARD PROCESSOR SYSTEM (HPS) .................................................................................................... 34
3.7.1
USER PUSH-BUTTONS, SWITCHES AND LED ON HPS ............................................................................................. 34
3.7.2
GIGABIT ETHERNET ............................................................................................................................................... 34
3.7.3
UART .................................................................................................................................................................... 36
3.7.4
DDR3 MEMORY ON HPS ....................................................................................................................................... 37
3.7.5
QSPI FLASH ........................................................................................................................................................... 39
3.7.6
MICRO SD .............................................................................................................................................................. 40
2
3.7.7 USB 2.0 OTG PHY ............................................................................................................................................... 40
3.7.8
G-SENSOR .............................................................................................................................................................. 41
3.7.9
128X64 DOTS LCD ................................................................................................................................................ 42
3.7.10
LTC CONNECTOR ................................................................................................................................................. 43
CHAPTER 4 SOCKIT SYSTEM BUILDER ..................................................................................................... 45
4.1 INTRODUCTION ......................................................................................................................................................... 45
4.2
GENERAL DESIGN FLOW ........................................................................................................................................... 45
4.3
USING SOCKIT SYSTEM BUILDER ............................................................................................................................. 46
CHAPTER 5 EXAMPLES FOR FPGA ............................................................................................................ 52
5.1 AUDIO RECORDING AND PLAYING ............................................................................................................................. 52
5.2
A KARAOKE MACHINE .............................................................................................................................................. 55
5.3
DDR3 SDRAM TEST ............................................................................................................................................... 58
5.4
DDR3 SDRAM TEST BY NIOS II .............................................................................................................................. 60
5.5
IR RECEIVER DEMONSTRATION ................................................................................................................................ 62
5.6
TEMPERATURE DEMONSTRATION .............................................................................................................................. 67
CHAPTER 6 STEPS OF PROGRAMMING THE QUAD SERIAL CONFIGURATION DEVICE ...................... 70
6.1 REVISION HISTORY ................................................................................................................................................... 70
CHAPTER 7 APPENDIX ................................................................................................................................. 77
7.1 REVISION HISTORY ................................................................................................................................................... 77
7.2
COPYRIGHT STATEMENT ........................................................................................................................................... 77
3
Chapter 1
SoCKit Development Kit
The SoCKit Development Kit presents a robust hardware design platform built around the Altera
System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores
with industry-leading programmable logic for ultimate design flexibility. Users can now leverage
the power of tremendous re-configurability paired with a high-performance, low-power processor
system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor,
peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth
interconnect backbone. The SoCKit development board includes hardware such as high-speed
DDR3 memory, video and audio capabilities, Ethernet networking, and much more. In addition, an
on-board HSMC connector with high-speed transceivers allows for an even greater array of
hardware setups. By leveraging all of these capabilities, the SoCKit is the perfect solution for
showcasing, evaluating, and prototyping the true potential of the Altera SoC.
The SoCKit Development Kit contains all components needed to use the board in conjunction with
a computer that runs the Microsoft Windows XP or later.
1
1
.
.
1
1
P
P
a
a
c
c
k
k
a
a
g
g
e
e
C
C
o
o
n
n
t
t
e
e
n
n
t
t
s
s
Figure 1-1 shows a photograph of the SoCKit package.
Figure 1-1 The SoCKit package contents
4
The SoCKit package includes:
• The SoCKit development board
• USB Cable for FPGA programming and control
• Ethernet Cable
• 12V DC power adapter
1
1
.
.
2
2
S
S
o
o
C
C
K
K
i
i
t
t
S
S
y
y
s
s
t
t
e
e
m
m
C
C
D
D
The SoCKit System CD containing the SoCKit documentation and supporting materials, including
the User Manual, System Builder, reference designs and device datasheets. User can download this
System CD form the link : http:/sockit_support.terasic.com.
1
1
.
.
3
3
G
G
e
e
t
t
t
t
i
i
n
n
g
g
H
H
e
e
l
l
p
p
For discussion, support, and reference designs, please go to:
RocketBoards.org
Arrow SoCKit Evaluation Board
Arrow SoCKIT Evaluation Board - How to Boot Linux
Here are the addresses where you can get help if you encounter any problem:
• Terasic Technologies
Taiwan/ 9F, No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, Taiwan 300-70
Email: support@terasic.com
Tel.: +886-3-5750-880
Web: http://sockit.terasic.com
5
Chapter 2
Introduction of the SoCKit
Board
This chapter presents the features and design characteristics of the board.
2
2
.
.
1
1
L
L
a
a
y
y
o
o
u
u
t
t
a
a
n
n
d
d
C
C
o
o
m
m
p
p
o
o
n
n
e
e
n
n
t
t
s
s
A photograph of the board is shown in Figure 2-1 and Figure 2-2. It depicts the layout of the board
and indicates the location of the connectors and key components.
JTAG Switch
Audio Codec
EPCQ 256Mb
HSMC Connector
Altera 28-nm Cyclone V FPGA
with ARM Cortex-A9
Clock Circuit for
FPGA and HPS
IR Receiver
FPGA Reset Key
HSMC Voltage-Level
Jumper
VGA
24-bit DAC
FPGA DDR3 1GB
Bottom Side Components:
*QSPI Flash 128MB
*Micro SD Card Socket
*FPGA Configuration Mode Switch
USB-UART
Port
JTAG
Header
USB 2.0 OTG
Port
Ethernet
10/100/1000
Port
VGA OUT
DB-15
Connector
Line
In
Mic
In
Line
Out
USB Blaster II
Port
12V DC Power Supply
Connector
LCD Backlight Jumper
128x64 Dots LCD
LTC Connector
TSE PHY
Power ON/OFF Switch
Altera USB Blaster II
Controller Chip
USB OTG Controller
(ULPI)
USB-UART Controller
CLKSEL Jumper
G-Sensor
HPS DDR3 1GB
HPS User KeysHPS System
Reset Keys
Temperature Sensor
FPGA User KeysFPGA User
Switches
FPGA User
LEDs
HPS User
Switches
HPS User
LEDs
BOOTSEL Jumper
HPS
FPGA
System
Figure 2-1 Development Board (top view)
6
Figure 2-2 Development Board (bottom view)
The board has many features that allow users to implement a wide range of designed circuits, from
simple circuits to various multimedia projects.
The following hardware is provided on the board:
F
F
P
P
G
G
A
A
D
D
e
e
v
v
i
i
c
c
e
e
• Cyclone V SoC 5CSXFC6D6F31 Device
• Dual-core ARM Cortex-A9 (HPS)
• 110K Programmable Logic Elements
• 5,140 Kbits embedded memory
• 6 Fractional PLLs
• 2 Hard Memory Controllers
• 3.125G Transceivers
7
C
C
o
o
n
n
f
f
i
i
g
g
u
u
r
r
a
a
t
t
i
i
o
o
n
n
a
a
n
n
d
d
D
D
e
e
b
b
u
u
g
g
• Quad Serial Configuration device – EPCQ256 on FPGA
• On-Board USB Blaster II (micro USB type B connector)
M
M
e
e
m
m
o
o
r
r
y
y
D
D
e
e
v
v
i
i
c
c
e
e
• 1GB (2x256MBx16) DDR3 SDRAM on FPGA
• 1GB (2x256MBx16) DDR3 SDRAM on HPS
• 128MB QSPI Flash on HPS
• Micro SD Card Socket on HPS
C
C
o
o
m
m
m
m
u
u
n
n
i
i
c
c
a
a
t
t
i
i
o
o
n
n
• USB 2.0 OTG (ULPI interface with micro USB type AB connector)
• USB to UART (micro USB type B connector)
• 10/100/1000 Ethernet
C
C
o
o
n
n
n
n
e
e
c
c
t
t
o
o
r
r
s
s
• One HSMC (8-channel Transceivers, Configurable I/O standards 1.5/1.8/2.5/3.3V)
• One LTC connector (One Serial Peripheral Interface (SPI) Master ,one I2C and one GPIO
interface )
D
D
i
i
s
s
p
p
l
l
a
a
y
y
• 24-bit VGA DAC
• 128x64 dots LCD Module with Backlight
A
A
u
u
d
d
i
i
o
o
• 24-bit CODEC, Line-in, line-out, and microphone-in jacks
S
S
w
w
i
i
t
t
c
c
h
h
e
e
s
s
,
,
B
B
u
u
t
t
t
t
o
o
n
n
s
s
a
a
n
n
d
d
L
L
E
E
D
D
s
s
• 8 User Keys (FPGA x4 ; HPS x 4)
• 8 User Switches (FPGA x4 ; HPS x 4)
• 8 User LEDs (FPGA x4 ; HPS x 4)
• 2 HPS Reset Buttons (HPS_RSET_n and HPS_WARM_RST_n)
8
S
S
e
e
n
n
s
s
o
o
r
r
s
s
• G-Sensor on HPS
• Temperature Sensor on FPGA
P
P
o
o
w
w
e
e
r
r
• 12V DC input
2
2
.
.
2
2
B
B
l
l
o
o
c
c
k
k
D
D
i
i
a
a
g
g
r
r
a
a
m
m
o
o
f
f
t
t
h
h
e
e
S
S
o
o
C
C
K
K
i
i
t
t
B
B
o
o
a
a
r
r
d
d
Figure 2-3 gives the block diagram of the board. To provide maximum flexibility for the user, all
connections are made through the Cyclone V SoC FPGA device. Thus, the user can configure the
FPGA to implement any system design.
9
Figure 2-3 Board Block Diagram
10
Chapter 3
Using the SoCKit Board
This chapter gives instructions for using the board and describes each of its peripherals.
3
3
.
.
1
1
B
B
o
o
a
a
r
r
d
d
S
S
e
e
t
t
u
u
p
p
C
C
o
o
m
m
p
p
o
o
n
n
e
e
n
n
t
t
s
s
The SoCKit includes several jumpers, switches, etc. that control various system functions including
JTAG chain, HSMC I/O voltage control, HPS boot source select, and others. This section will
explain the settings and functions in detail.
3
3
.
.
1
1
.
.
1
1
J
J
T
T
A
A
G
G
C
C
h
h
a
a
i
i
n
n
a
a
n
n
d
d
S
S
e
e
t
t
u
u
p
p
S
S
w
w
i
i
t
t
c
c
h
h
e
e
s
s
The SoCKit allows users to access the FPGA, HPS debug, or other JTAG chain devices via the
on-board USB Blaster II. Figure 3-1 shows the JTAG chain. Users can control whether the HPS or
HSMC connector is included in the JTAG chain via SW4 (See Figure 3-2), where Table 3-1 lists
the configuration details
11
Figure 3-1 The JTAG chain on the board
Figure 3-2 JTAG Chain and Setup Switches
Table 3-1 SW4 JTAG Control DIP Switch
Board Reference
Signal Name
Description
Default
SW4.1 JTAG_HPS_EN
On: Bypass HPS
Off: HPS In-chain
Off
SW4.2 JTAG_HSMC_EN
On: Bypass HSMC
Off: HSMC In-chain
On
12
3
3
.
.
1
1
.
.
2
2
F
F
P
P
G
G
A
A
C
C
o
o
n
n
f
f
i
i
g
g
u
u
r
r
a
a
t
t
i
i
o
o
n
n
M
M
o
o
d
d
e
e
S
S
w
w
i
i
t
t
c
c
h
h
The Dipswitch SW6 (See Figure 3-3) can set the MSEL pins to decide the FPGA configuration
modes. Table 3-2 shows the switch controls and descriptions. Table 3-3 gives the MSEL pins
setting for each configuration scheme of Cyclone V devices. FPGA default works in ASx4 mode.
However, once the FPGA is in AS x4 mode, and after successfully configuring the FPGA via the
EPCQ256, the SoCKit will be unable to boot Linux from the SD card or other devices. Please
switch SW6 to another mode (i.e. MSEL[0:4] = 00001) to enable normal operations of Linux.
Figure 3-3 FPGA Configuration Mode Switch
Table 3-2 SW6 FPGA Configuration Mode Switch
Board Reference Signal Name Description Default
SW6.1
MSEL0
Sets the Cyclone V MSEL[0:4] pins.
Use these pins to set the configuration
scheme and POR delay.
On
SW6.2
MSEL1
Off
SW6.3
MSEL2
On
SW6.4
MSEL3
On
SW6.5
MSEL4
Off
SW6.6
N/A
N/A
N/A
Table 3-3 MSEL pin Settings for each Scheme of Cyclone V Device
Configuration
Scheme
Compression Feature
Design Security
Feature
POR Delay
Valid MSEL[4:0]
FPPx8
Disabled Disabled
Fast
10100
Standard
11000
Disabled
Enabled
Fast
10101
13
Standard
11001
Enabled Disabled
Fast
10110
Standard
11010
FPPx16
Disabled Enabled
Fast
00000
Standard
00100
Disabled Disabled
Fast
00001
Standard
00101
Enabled Enabled
Fast
00010
Standard
00110
PS Enabled/ Disabled Disabled
Fast
10000
Standard
10001
AS(X1 and X4) Enabled/ Disabled Enabled
Fast
10010
Standard
10011
3
3
.
.
1
1
.
.
3
3
H
H
P
P
S
S
B
B
O
O
O
O
T
T
S
S
E
E
L
L
a
a
n
n
d
d
C
C
L
L
K
K
S
S
E
E
L
L
S
S
e
e
t
t
t
t
i
i
n
n
g
g
H
H
e
e
a
a
d
d
e
e
r
r
s
s
The processor in the HPS can be boot from many sources such as the SD card, QSPI Flash or FPGA.
Selecting the boot source for the HPS can be set using the BOOTSEL jumpers (J17~J19, See
Figure 3-4) and CLKSEL jumpers (J15~J16, See Figure 3-5). Table 3-4 lists BOOTSEL and
CLKSEL settings. Table 3-5 lists the settings for selecting a suitable boot source.
Figure 3-4 HPS BOOTSEL Setting Headers
14
Figure 3-5 HPS CLKSEL Setting Headers
Table 3-4 HPS BOOTSEL and CLKSEL Setting Headers
Board Reference Signal Name Setting Default
J17 BOOTSEL0
Short Pin 1 and 2: Logic 1
Short Pin 2 and 3: Logic 0
Short Pin 1 and 2
J19 BOOTSEL1
Short Pin 1 and 2: Logic 1
Short Pin 2 and 3: Logic 0
Short Pin 2 and 3
J18 BOOTSEL2
Short Pin 1 and 2: Logic 1
Short Pin 2 and 3: Logic 0
Short Pin 1 and 2
J15 CLKSEL0
Short Pin 1 and 2: Logic 1
Short Pin 2 and 3: Logic 0
Short Pin 2 and 3
J16 CLKSEL1
Short Pin 1 and 2: Logic 1
Short Pin 2 and 3: Logic 0
Short Pin 2 and 3
Table 3-5 BOOTSEL[2:0] Setting Values and Flash Device Selection
BOOTSEL[2:0] Setting Value
Flash Deice
000
Reserved
001
FPGA (HPS-to-FPGA bridge)
010
1.8 V NAMD Flash memory (*1)
011
3.0 V NAMD Flash memory(*1)
100
1.8 V SD/MMC Flash memory(*1)
101
3.0 V SD/MMC Flash memory
110
1.8 V SPI or quad SPI Flash memory(*1)
111
3.0 V SPI or quad SPI Flash memory
(*1) : Not supported on SoCKit board
15
3
3
.
.
1
1
.
.
4
4
H
H
S
S
M
M
C
C
V
V
C
C
C
C
I
I
O
O
V
V
o
o
l
l
t
t
a
a
g
g
e
e
L
L
e
e
v
v
e
e
l
l
S
S
e
e
t
t
t
t
i
i
n
n
g
g
H
H
e
e
a
a
d
d
e
e
r
r
On the SoCKit, the I/O standards of the FPGA/HSMC pins can be adjusted via JP2 (See Figure
3-6). Adjustable standards allow even more flexibility and selection of daughter cards or
interconnect devices.
The HSMC connector’s default standard is 2.5V. Users must ensure that the voltage standards for
both the main board and daughter card are the same, or damage/incompatibility may occur.
Table 3-6 lists JP2 settings.
Figure 3-6 HSMC VCCIO Voltage Level Setting Header
Table 3-6 JP2 Header Setting for Different I/O Standard
JP2 Jumper Setting
I/O Voltage of HSMC Connector
Short Pin 1 and 2
1.5V
Short Pin 3 and 4
1.8V
Short Pin 5 and 6
2.5V (Default)
Short Pin 7 and 8
3.3V
Note:
1. JP2 only allows for one jumper at one time.
2. If no jumper is attached on JP2, the voltage standard will default to 1.5V
3
3
.
.
2
2
B
B
o
o
a
a
r
r
d
d
S
S
t
t
a
a
t
t
u
u
s
s
E
E
l
l
e
e
m
m
e
e
n
n
t
t
s
s
The board includes status LEDs. Please refer to Table 3-7 for the status of the LED indicator.
16
Table 3-7 LED Indicators
Board Reference
LED Name
Description
D5 12-V Power Illuminates when 12-V power is active.
TXD UART TXD Illuminates when data from FT232R to USB Host.
RXD UART RXD
Illuminates when data from USB Host to FT232R.
D9 HSMC PSNTN
Illuminates when connecting a daughter card on HSMC
connector.
D1 JTAG_RX
Reserved
D2 JTAG_TX
D3 SC_RX
D4 SC_TX
3
3
.
.
3
3
B
B
o
o
a
a
r
r
d
d
R
R
e
e
s
s
e
e
t
t
E
E
l
l
e
e
m
m
e
e
n
n
t
t
s
s
The board equips two HPS reset circuits and one FPGA Device Clear button (See Figure 3-7).
Table 3-8 shows the buttons references and its descriptions. Figure 3-8 shows the reset tree on the
board.
Figure 3-7 Board Reset Elements
17
Table 3-8 Reset Elements
Board Reference Signal Name Description
KEY5 HPS_RESET_n
Cold reset to the HPS , Ethernet PHY, UART and USB OTG
device . Active low input that will reset all HPS logics that can
be reset. Places the HPS in a default state sufficient for
software to boot.
KEY6
HPS_WARM_RST_n
Warm reset to the HPS block. Active low input affects the
system reset domains which allows debugging to operate.
KEY4 FPGA_RESET_n
This signal connects to the Cyclone V DEV_CLRn pin. When
this pin is driven low, all the device registers are.
Figure 3-8 Reset Tree on the Development Board
3
3
.
.
4
4
P
P
r
r
o
o
g
g
r
r
a
a
m
m
m
m
i
i
n
n
g
g
t
t
h
h
e
e
Q
Q
u
u
a
a
d
d
-
-
S
S
e
e
r
r
i
i
a
a
l
l
C
C
o
o
n
n
f
f
i
i
g
g
u
u
r
r
a
a
t
t
i
i
o
o
n
n
D
D
e
e
v
v
i
i
c
c
e
e
• The board contains a quad serial configuration device (EPCQ256) that stores configuration data
for the Cyclone V SoC FPGA. This configuration data is automatically loaded from the quad
18
serial configuration device chip into the FPGA when the board is powered up.
• To program the configuration device, users will need to use a Serial Flash Loader (SFL)
function to program the quad serial configuration device via the JTAG interface. The
FPGA-based SFL is a soft intellectual property (IP) core within the FPGA that bridges the JTAG
and flash interfaces. The SFL mega-function is available from Quartus II software. Figure 3-9
shows the programming method when adopting a SFL solution
• Please refer to Chapter 6: Steps of Programming the Quad Serial Configuration Device for the
basic programming instruction on the serial configuration device
Figure 3-9 Programming a Quad Serial Configuration Device with the SFL Solution
Note: Before programming the quad serial configuration device, please set the FPGA
configuration mode switch (SW6) to ASx4 mode.
3
3
.
.
5
5
C
C
l
l
o
o
c
c
k
k
C
C
i
i
r
r
c
c
u
u
i
i
t
t
s
s
Figure 3-10 is a diagram showing the default frequencies of all of the external clocks going to the
Cyclone V SoC FPGA.
19
Figure 3-10 Block diagram of the clock distribution
3
3
.
.
6
6
I
I
n
n
t
t
e
e
r
r
f
f
a
a
c
c
e
e
o
o
n
n
F
F
P
P
G
G
A
A
This section describes the interfaces to the FPGA. Users can control or monitor the different interfaces with user
logic on the FPGA.
3.6.1 User Push-buttons, Switches and LED on FPGA
The board provides four push-button switches connected to FPGA as shown in Figure 3-11. Each of
these switches is debounced using a Schmitt Trigger circuit, as indicated in Figure 3-12. The four
outputs called KEY0, KEY1, KEY2, and KEY3 of the Schmitt Trigger devices are connected
directly to the Cyclone V SoC FPGA. Each push-button switch provides a high logic level when it
is not pressed, and provides a low logic level when depressed. Since the push-button switches are
debounced, they are appropriate for using as clock or reset inputs in a circuit.
20
Figure 3-11 Connections between the push-button and Cyclone V SoC FPGA
Pushbutton released
Pushbutton depressed
Before
Debouncing
Schmitt Trigger
Debounced
Figure 3-12 Switch debouncing
There are four slide switches connected to FPGA on the board (See Figure 3-13). These switches
are not debounced, and are assumed for use as level-sensitive data inputs to a circuit. Each switch is
connected directly to a pin on the Cyclone V SoC FPGA. When the switch is in the DOWN position
(closest to the edge of the board), it provides a low logic level to the FPGA, and when the switch is
in the UP position it provides a high logic level.
21
Figure 3-13 Connections between the slide switches and Cyclone V SoC FPGA
There are also four user-controllable LEDs connected to FPGA on the board. Each LED is driven
directly by a pin on the Cyclone V SoC FPGA; driving its associated pin to a high logic level turns
the LED on, and driving the pin low turns it off. Figure 3-14 shows the connections between LEDs
and Cyclone V SoC FPGA. Table 3-9, Table 3-10 and Table 3-11 list the pin assignments of these
user interfaces.
Figure 3-14 Connections between the LEDs and Cyclone V SoC FPGA
22
Table 3-9 Pin Assignments for Slide Switches
Signal Name FPGA Pin No. Description I/O Standard
SW[0]
PIN_W25
Slide Switch[0]
2.5V
SW[1]
PIN_V25
Slide Switch[1]
2.5V
SW[2]
PIN_AC28
Slide Switch[2]
2.5V
SW[3]
PIN_AC29
Slide Switch[3]
2.5V
Table 3-10 Pin Assignments for Push-buttons
Signal Name
FPGA Pin No.
Description
I/O Standard
KEY[0] PIN_AE9 Push-button[0] 3.3V
KEY[1]
PIN_AE12
Push-button[1]
3.3V
KEY[2]
PIN_AD9
Push-button[2]
3.3V
KEY[3]
PIN_AD11
Push-button[3]
3.3V
Table 3-11 Pin Assignments for LEDs
Signal Name
FPGA Pin No.
Description
I/O Standard
LED[0]
PIN_AF10
LED [0]
3.3V
LED[1]
PIN_AD10
LED [1]
3.3V
LED[2]
PIN_AE11
LED [2]
3.3V
LED[3]
PIN_AD7
LED [3]
3.3V
3.6.2 HSMC connector
The board contains a High Speed Mezzanine Card (HSMC) interface to provide a mechanism for
extending the peripheral-set of an FPGA host board by means of add-on daughter cards, which can
address today’s high speed signaling requirements as well as low-speed device interface support.
The HSMC interface support JTAG, clock outputs and inputs, high-speed serial I/O (transceivers),
and single-ended or differential signaling. Signals on the HSMC port are shown in Figure 3-15.
Table 3-12 shows the maximum power consumption of the daughter card that connects to HSMC
port.
23
Figure 3-15 HSMC Signal Bank Diagram
Table 3-12 Power Supply of the HSMC
Supplied Voltage Max. Current Limit
12V
1A
3.3V
1.5A
Table 3-13 Pin Assignments for HSMC connector
Signal Name
FPGA Pin No.
Description
I/O Standard
HSMC_CLK_IN0
PIN_J14
Dedicated clock input
Depend on JP2
HSMC_CLKIN_n1 PIN_AB27 LVDS RX or CMOS I/O or
differential clock input
Depend on JP2
HSMC_CLKIN_n2 PIN_G15 LVDS RX or CMOS I/O or
differential clock input
Depend on JP2
HSMC_CLKIN_p1 PIN_AA26 LVDS RX or CMOS I/O or
differential clock input
Depend on JP2
HSMC_CLKIN_p2 PIN_H15 LVDS RX or CMOS I/O or
differential clock input
Depend on JP2
HSMC_CLK_OUT0
PIN_AD29
Dedicated clock output
Depend on JP2
HSMC_CLKOUT_n1 PIN_E6 LVDS TX or CMOS I/O or
differential clock input/output
Depend on JP2
HSMC_CLKOUT_n2 PIN_A10 LVDS TX or CMOS I/O or
differential clock input/output
Depend on JP2
HSMC_CLKOUT_p1
PIN_E7
LVDS TX or CMOS I/O or
Depend on JP2
24
differential clock input/output
HSMC_CLKOUT_p2 PIN_A11 LVDS TX or CMOS I/O or
differential clock input/output
Depend on JP2
HSMC_D[0]
PIN_C10
LVDS TX or CMOS I/O
Depend on JP2
HSMC_D[1]
PIN_H13
LVDS RX or CMOS I/O
Depend on JP2
HSMC_D[2]
PIN_C9
LVDS TX or CMOS I/O
Depend on JP2
HSMC_D[3]
PIN_H12
LVDS RX or CMOS I/O
Depend on JP2
HSMC_SCL
PIN_AA28
Management serial data
Depend on JP2
HSMC_SDA
PIN_AE29
Management serial clock
Depend on JP2
HSMC_GXB_RX_p[0]
PIN_AE2
Transceiver RX bit 0
1.5-V PCML
HSMC_GXB_RX_p[1]
PIN_AC2
Transceiver RX bit 1
1.5-V PCML
HSMC_GXB_RX_p[2]
PIN_AA2
Transceiver RX bit 2
1.5-V PCML
HSMC_GXB_RX_p[3]
PIN_W2
Transceiver RX bit 3
1.5-V PCML
HSMC_GXB_RX_p[4]
PIN_U2
Transceiver RX bit 4
1.5-V PCML
HSMC_GXB_RX_p[5]
PIN_R2
Transceiver RX bit 5
1.5-V PCML
HSMC_GXB_RX_p[6]
PIN_N2
Transceiver RX bit 6
1.5-V PCML
HSMC_GXB_RX_p[7]
PIN_J2
Transceiver RX bit 7
1.5-V PCML
HSMC_GXB_TX_p[0]
PIN_AD4
Transceiver TX bit 0
1.5-V PCML
HSMC_GXB_TX_p[1]
PIN_AB4
Transceiver TX bit 1
1.5-V PCML
HSMC_GXB_TX_p[2]
PIN_Y4
Transceiver TX bit 2
1.5-V PCML
HSMC_GXB_TX_p[3]
PIN_V4
Transceiver TX bit 3
1.5-V PCML
HSMC_GXB_TX_p[4]
PIN_T4
Transceiver TX bit 4
1.5-V PCML
HSMC_GXB_TX_p[5]
PIN_P4
Transceiver TX bit 5
1.5-V PCML
HSMC_GXB_TX_p[6]
PIN_M4
Transceiver TX bit 6
1.5-V PCML
HSMC_GXB_TX_p[7]
PIN_H4
Transceiver TX bit 7
1.5-V PCML
HSMC_GXB_RX_n[0]
PIN_AE1
Transceiver RX bit 0n
1.5-V PCML
HSMC_GXB_RX_n[1]
PIN_AC1
Transceiver RX bit 1n
1.5-V PCML
HSMC_GXB_RX_n[2]
PIN_AA1
Transceiver RX bit 2n
1.5-V PCML
HSMC_GXB_RX_n[3]
PIN_W1
Transceiver RX bit 3n
1.5-V PCML
HSMC_GXB_RX_n[4]
PIN_U1
Transceiver RX bit 4n
1.5-V PCML
HSMC_GXB_RX_n[5]
PIN_R1
Transceiver RX bit 5n
1.5-V PCML
HSMC_GXB_RX_n[6]
PIN_N1
Transceiver RX bit 6n
1.5-V PCML
HSMC_GXB_RX_n[7]
PIN_J1
Transceiver RX bit 7n
1.5-V PCML
HSMC_GXB_TX_n[0]
PIN_AD3
Transceiver TX bit 0n
1.5-V PCML
HSMC_GXB_TX_n[1]
PIN_AB3
Transceiver TX bit 1n
1.5-V PCML
HSMC_GXB_TX_n[2]
PIN_Y3
Transceiver TX bit 2n
1.5-V PCML
HSMC_GXB_TX_n[3]
PIN_V3
Transceiver TX bit 3n
1.5-V PCML
HSMC_GXB_TX_n[4]
PIN_T3
Transceiver TX bit 4n
1.5-V PCML
HSMC_GXB_TX_n[5]
PIN_P3
Transceiver TX bit 5n
1.5-V PCML
HSMC_GXB_TX_n[6]
PIN_M3
Transceiver TX bit 6n
1.5-V PCML
HSMC_GXB_TX_n[7]
PIN_H3
Transceiver TX bit 7n
1.5-V PCML
HSMC_RX _n[0]
PIN_G11
LVDS RX bit 0n or CMOS I/O
Depend on JP2
HSMC_RX _n[1]
PIN_J12
LVDS RX bit 1n or CMOS I/O
Depend on JP2
HSMC_RX _n[2]
PIN_F10
LVDS RX bit 2n or CMOS I/O
Depend on JP2
HSMC_RX _n[3]
PIN_J9
LVDS RX bit 3n or CMOS I/O
Depend on JP2
HSMC_RX _n[4]
PIN_K8
LVDS RX bit 4n or CMOS I/O
Depend on JP2
25
HSMC_RX _n[5]
PIN_H7
LVDS RX bit 5n or CMOS I/O
Depend on JP2
HSMC_RX _n[6]
PIN_G8
LVDS RX bit 6n or CMOS I/O
Depend on JP2
HSMC_RX _n[7]
PIN_F8
LVDS RX bit 7n or CMOS I/O
Depend on JP2
HSMC_RX _n[8]
PIN_E11
LVDS RX bit 8n or CMOS I/O
Depend on JP2
HSMC_RX _n[9]
PIN_B5
LVDS RX bit 9n or CMOS I/O
Depend on JP2
HSMC_RX _n[10]
PIN_D9
LVDS RX bit 10n or CMOS I/O
Depend on JP2
HSMC_RX _n[11]
PIN_D12
LVDS RX bit 11n or CMOS I/O
Depend on JP2
HSMC_RX _n[12]
PIN_D10
LVDS RX bit 12n or CMOS I/O
Depend on JP2
HSMC_RX _n[13]
PIN_B12
LVDS RX bit 13n or CMOS I/O
Depend on JP2
HSMC_RX _n[14]
PIN_E13
LVDS RX bit 14n or CMOS I/O
Depend on JP2
HSMC_RX _n[15]
PIN_G13
LVDS RX bit 15n or CMOS I/O
Depend on JP2
HSMC_RX _n[16]
PIN_F14
LVDS RX bit 16n or CMOS I/O
Depend on JP2
HSMC_RX _p[0]
PIN_G12
LVDS RX bit 0 or CMOS I/O
Depend on JP2
HSMC_RX _p[1]
PIN_K12
LVDS RX bit 1 or CMOS I/O
Depend on JP2
HSMC_RX _p[2]
PIN_G10
LVDS RX bit 2 or CMOS I/O
Depend on JP2
HSMC_RX _p[3]
PIN_J10
LVDS RX bit 3 or CMOS I/O
Depend on JP2
HSMC_RX _p[4]
PIN_K7
LVDS RX bit 4 or CMOS I/O
Depend on JP2
HSMC_RX _p[5]
PIN_J7
LVDS RX bit 5 or CMOS I/O
Depend on JP2
HSMC_RX _p[6]
PIN_H8
LVDS RX bit 6 or CMOS I/O
Depend on JP2
HSMC_RX _p[7]
PIN_F9
LVDS RX bit 7 or CMOS I/O
Depend on JP2
HSMC_RX _p[8]
PIN_F11
LVDS RX bit 8 or CMOS I/O
Depend on JP2
HSMC_RX _p[9]
PIN_B6
LVDS RX bit 9 or CMOS I/O
Depend on JP2
HSMC_RX _p[10]
PIN_E9
LVDS RX bit 10 or CMOS I/O
Depend on JP2
HSMC_RX _p[11]
PIN_E12
LVDS RX bit 11 or CMOS I/O
Depend on JP2
HSMC_RX _p[12]
PIN_D11
LVDS RX bit 12 or CMOS I/O
Depend on JP2
HSMC_RX _p[13]
PIN_C13
LVDS RX bit 13 or CMOS I/O
Depend on JP2
HSMC_RX _p[14]
PIN_F13
LVDS RX bit 14 or CMOS I/O
Depend on JP2
HSMC_RX _p[15]
PIN_H14
LVDS RX bit 15 or CMOS I/O
Depend on JP2
HSMC_RX _p[16]
PIN_F15
LVDS RX bit 16 or CMOS I/O
Depend on JP2
HSMC_TX _n[0]
PIN_A8
LVDS TX bit 0n or CMOS I/O
Depend on JP2
HSMC_TX _n[1]
PIN_D7
LVDS TX bit 1n or CMOS I/O
Depend on JP2
HSMC_TX _n[2]
PIN_F6
LVDS TX bit 2n or CMOS I/O
Depend on JP2
HSMC_TX _n[3]
PIN_C5
LVDS TX bit 3n or CMOS I/O
Depend on JP2
HSMC_TX _n[4]
PIN_C4
LVDS TX bit 4n or CMOS I/O
Depend on JP2
HSMC_TX _n[5]
PIN_E2
LVDS TX bit 5n or CMOS I/O
Depend on JP2
HSMC_TX _n[6]
PIN_D4
LVDS TX bit 6n or CMOS I/O
Depend on JP2
HSMC_TX _n[7]
PIN_B3
LVDS TX bit 7n or CMOS I/O
Depend on JP2
HSMC_TX _n[8]
PIN_D1
LVDS TX bit 8n or CMOS I/O
Depend on JP2
HSMC_TX _n[9]
PIN_C2
LVDS TX bit 9n or CMOS I/O
Depend on JP2
HSMC_TX _n[10]
PIN_B1
LVDS TX bit 10n or CMOS I/O
Depend on JP2
HSMC_TX _n[11]
PIN_A3
LVDS TX bit 11n or CMOS I/O
Depend on JP2
HSMC_TX _n[12]
PIN_A5
LVDS TX bit 12n or CMOS I/O
Depend on JP2
HSMC_TX _n[13]
PIN_B7
LVDS TX bit 13n or CMOS I/O
Depend on JP2
HSMC_TX _n[14]
PIN_B8
LVDS TX bit 14n or CMOS I/O
Depend on JP2
HSMC_TX _n[15]
PIN_B11
LVDS TX bit 15n or CMOS I/O
Depend on JP2
HSMC_TX _n[16]
PIN_A13
LVDS TX bit 16n or CMOS I/O
Depend on JP2
26
HSMC_TX _p[0]
PIN_A9
LVDS TX bit 0 or CMOS I/O
Depend on JP2
HSMC_TX _p[1]
PIN_E8
LVDS TX bit 1 or CMOS I/O
Depend on JP2
HSMC_TX _p[2]
PIN_G7
LVDS TX bit 2 or CMOS I/O
Depend on JP2
HSMC_TX _p[3]
PIN_D6
LVDS TX bit 3 or CMOS I/O
Depend on JP2
HSMC_TX _p[4]
PIN_D5
LVDS TX bit 4 or CMOS I/O
Depend on JP2
HSMC_TX _p[5]
PIN_E3
LVDS TX bit 5 or CMOS I/O
Depend on JP2
HSMC_TX _p[6]
PIN_E4
LVDS TX bit 6 or CMOS I/O
Depend on JP2
HSMC_TX _p[7]
PIN_C3
LVDS TX bit 7 or CMOS I/O
Depend on JP2
HSMC_TX _p[8]
PIN_E1
LVDS TX bit 8 or CMOS I/O
Depend on JP2
HSMC_TX _p[9]
PIN_D2
LVDS TX bit 9 or CMOS I/O
Depend on JP2
HSMC_TX _p[10]
PIN_B2
LVDS TX bit 10 or CMOS I/O
Depend on JP2
HSMC_TX _p[11]
PIN_A4
LVDS TX bit 11 or CMOS I/O
Depend on JP2
HSMC_TX _p[12]
PIN_A6
LVDS TX bit 12 or CMOS I/O
Depend on JP2
HSMC_TX _p[13]
PIN_C7
LVDS TX bit 13 or CMOS I/O
Depend on JP2
HSMC_TX _p[14]
PIN_C8
LVDS TX bit 14 or CMOS I/O
Depend on JP2
HSMC_TX _p[15]
PIN_C12
LVDS TX bit 15 or CMOS I/O
Depend on JP2
HSMC_TX _p[16]
PIN_B13
LVDS TX bit 16 or CMOS I/O
Depend on JP2
3.6.3 Audio CODEC
The board provides high-quality 24-bit audio via the Analog Devices SSM2603 audio CODEC
(Encoder/Decoder). This chip supports microphone-in, line-in, and line-out ports, with a sample rate
adjustable from 8 kHz to 96 kHz. The SSM2603 is controlled via a serial I2C bus interface, which
is connected to pins on the Cyclone V SoC FPGA. A schematic diagram of the audio circuitry is
shown in Figure 3-16. Detailed information for using the SSM2603 codec is available in its
datasheet, which can be found on the manufacturer’s website, or in the Datasheets\Audio CODEC
folder on the SoCKit System CD
Figure 3-16 Connections between FPGA and Audio CODEC
27
Table 3-14 Pin Assignments for Audio CODEC
Signal Name
FPGA Pin No.
Description
I/O Standard
AUD_ADCLRCK
PIN_AG30
Audio CODEC ADC LR Clock
3.3V
AUD_ADCDAT
PIN_AC27
Audio CODEC ADC Data
3.3V
AUD_DACLRCK
PIN_AH4
Audio CODEC DAC LR Clock
3.3V
AUD_DACDAT
PIN_AG3
Audio CODEC DAC Data
3.3V
AUD_XCK
PIN_AC9
Audio CODEC Chip Clock
3.3V
AUD_BCLK
PIN_AE7
Audio CODEC Bit-Stream Clock
3.3V
AUD_I2C_SCLK
PIN_AH30
I2C Clock
3.3V
AUD_I2C_SDAT
PIN_AF30
I2C Data
3.3V
AUD_MUTE
PIN_AD26
DAC Output Mute, Active Low
3.3V
3.6.4 VGA
The board includes a 15-pin D-SUB connector for VGA output. The VGA synchronization signals
are provided directly from the Cyclone V SoC FPGA, and the Analog Devices ADV7123 triple
10-bit high-speed video DAC (only the higher 8-bits are used) is used to produce the analog data
signals (red, green, and blue). It could support the SXGA standard (1280*1024) with a bandwidth
of 100MHz. Figure 3-17 gives the associated schematic.
Figure 3-17 VGA Connections between FPGA and VGA
The timing specification for VGA synchronization and RGB (red, green, blue) data can be found on
various educational website (for example, search for “VGA signal timing”). Figure 3-18 illustrates
the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor. An
active-low pulse of specific duration (time (a) in the figure) is applied to the horizontal
synchronization (hsync) input of the monitor, which signifies the end of one row of data and the
28
start of the next. The data (RGB) output to the monitor must be off (driven to 0 V) for a time period
called the back porch (b) after the hsync pulse occurs, which is followed by the display interval (c).
During the data display interval the RGB data drives each pixel in turn across the row being
displayed. Finally, there is a time period called the front porch (d) where the RGB signals must
again be off before the next hsync pulse can occur. The timing of the vertical synchronization
(vsync) is the similar as shown in Figure 3-18, except that a vsync pulse signifies the end of one
frame and the start of the next, and the data refers to the set of rows in the frame (horizontal timing).
Table 3-15 and Table 3-16 show different resolutions and durations of time periods a, b, c, and d
for both horizontal and vertical timing.
Detailed information for using the ADV7123 video DAC is available in its datasheet, which can be
found on the manufacturer’s website, or in the Datasheets\VIDEO DAC folder on the SoCKit
System CD. The pin assignments between the Cyclone V SoC FPGA and the ADV7123 are listed in
Table 3-17
Figure 3-18 VGA horizontal timing specification
Table 3-15 VGA Horizontal Timing Specification
VGA mode Horizontal Timing Spec
Configuration
Resolution(HxV)
a(us)
b(us)
c(us)
d(us)
Pixel clock(MHz)
VGA(60Hz) 640x480 3.8 1.9 25.4 0.6 25
VGA(85Hz) 640x480 1.6 2.2 17.8 1.6 36
SVGA(60Hz) 800x600 3.2 2.2 20 1 40
SVGA(75Hz) 800x600 1.6 3.2 16.2 0.3 49
SVGA(85Hz) 800x600 1.1 2.7 14.2 0.6 56
XGA(60Hz) 1024x768 2.1 2.5 15.8 0.4 65
XGA(70Hz) 1024x768 1.8 1.9 13.7 0.3 75
XGA(85Hz) 1024x768 1.0 2.2 10.8 0.5 95
1280x1024(60Hz) 1280x1024 1.0 2.3 11.9 0.4 108
29
Table 3-16 VGA Vertical Timing Specification
VGA mode
Vertical Timing Spec
Configuration Resolution(HxV) a(lines) b(lines) c(lines) d(lines) Pixel clock(MHz)
VGA(60Hz)
640x480
2
33
480
10
25
VGA(85Hz)
640x480
3
25
480
1
36
SVGA(60Hz)
800x600
4
23
600
1
40
SVGA(75Hz)
800x600
3
21
600
1
49
SVGA(85Hz)
800x600
3
27
600
1
56
XGA(60Hz)
1024x768
6
29
768
3
65
XGA(70Hz)
1024x768
6
29
768
3
75
XGA(85Hz)
1024x768
3
36
768
1
95
1280x1024(60Hz)
1280x1024
3
38
1024
1
108
Table 3-17 Pin Assignments for VGA
Signal Name
FPGA Pin No.
Description
I/O Standard
VGA_R[0]
PIN_AG5
VGA Red[0]
3.3V
VGA_R[1]
PIN_AA12
VGA Red[1]
3.3V
VGA_R[2]
PIN_AB12
VGA Red[2]
3.3V
VGA_R[3]
PIN_AF6
VGA Red[3]
3.3V
VGA_R[4]
PIN_AG6
VGA Red[4]
3.3V
VGA_R[5]
PIN_AJ2
VGA Red[5]
3.3V
VGA_R[6]
PIN_AH5
VGA Red[6]
3.3V
VGA_R[7]
PIN_AJ1
VGA Red[7]
3.3V
VGA_G[0]
PIN_Y21
VGA Green[0]
3.3V
VGA_G[1]
PIN_AA25
VGA Green[1]
3.3V
VGA_G[2]
PIN_AB26
VGA Green[2]
3.3V
VGA_G[3]
PIN_AB22
VGA Green[3]
3.3V
VGA_G[4]
PIN_AB23
VGA Green[4]
3.3V
VGA_G[5]
PIN_AA24
VGA Green[5]
3.3V
VGA_G[6]
PIN_AB25
VGA Green[6]
3.3V
VGA_G[7]
PIN_AE27
VGA Green[7]
3.3V
VGA_B[0]
PIN_AE28
VGA Blue[0]
3.3V
VGA_B[1]
PIN_Y23
VGA Blue[1]
3.3V
VGA_B[2]
PIN_Y24
VGA Blue[2]
3.3V
VGA_B[3]
PIN_AG28
VGA Blue[3]
3.3V
VGA_B[4]
PIN_AF28
VGA Blue[4]
3.3V
VGA_B[5]
PIN_V23
VGA Blue[5]
3.3V
VGA_B[6]
PIN_W24
VGA Blue[6]
3.3V
VGA_B[7]
PIN_AF29
VGA Blue[7]
3.3V
VGA_CLK
PIN_W20
VGA Clock
3.3V
VGA_BLANK_n
PIN_AH3
VGA BLANK
3.3V
VGA_HS
PIN_AD12
VGA H_SYNC
3.3V
VGA_VS
PIN_AC12
VGA V_SYNC
3.3V
VGA_SYNC_n
PIN_AG2
VGA SYNC
3.3V
30
3.6.5 IR Receiver
The board provides an infrared remote-control receiver module (model: IRM-V5XX/TR1), whose
datasheet is offered in the Datasheets\IR_Receiver folder on SoCKit System CD. The accompanied
remote controller with an encoding chip of uPD6121G is very suitable of generating expected
infrared signals. Figure 3-19 shows the related schematic of the IR receiver. Table 3-18 shows the
IR receiver interface pin assignments.
Figure 3-19 Connection between FPGA and IR
Table 3-18 Pin Assignments for IR
Signal Name
FPGA Pin No.
Description
I/O Standard
IRDA_RXD
PIN_ AH2
IR Receiver
3.3V
3.6.6 DDR3 Memory on FPGA
The board supports 1GB of DDR3 SDRAM comprising of two x16 bit DDR3 devices on FPGA
side. The DDR3 devices shipped with this board are running at 400MHz if the hard external
memory interface is enabled, and at 300MHz if the hard external memory interface if not enabled.
Figure 3-20 shows the connections between the DDR3 and Cyclone V SoC FPGA. Table 3-19
shows the DDR3 interface pin assignments.
31
Figure 3-20 Connections between FPGA and DDR3
Table 3-19 Pin Assignments for DDR3
Signal Name
FPGA Pin No.
Description
I/O Standard
DDR3_A[0] PIN_AJ14 DDR3 Address[0] SSTL-15 Class I
DDR3_A[1]
PIN_AK14
DDR3 Address[1]
SSTL-15 Class I
DDR3_A[2]
PIN_AH12
DDR3 Address[2]
SSTL-15 Class I
DDR3_A[3]
PIN_AJ12
DDR3 Address[3]
SSTL-15 Class I
DDR3_A[4]
PIN_AG15
DDR3 Address[4]
SSTL-15 Class I
DDR3_A[5]
PIN_AH15
DDR3 Address[5]
SSTL-15 Class I
DDR3_A[6] PIN_AK12 DDR3 Address[6] SSTL-15 Class I
DDR3_A[7]
PIN_AK13
DDR3 Address[7]
SSTL-15 Class I
DDR3_A[8]
PIN_AH13
DDR3 Address[8]
SSTL-15 Class I
DDR3_A[9]
PIN_AH14
DDR3 Address[9]
SSTL-15 Class I
DDR3_A[10]
PIN_AJ9
DDR3 Address[10]
SSTL-15 Class I
DDR3_A[11]
PIN_AK9
DDR3 Address[11]
SSTL-15 Class I
DDR3_A[12] PIN_AK7 DDR3 Address[12] SSTL-15 Class I
DDR3_A[13]
PIN_AK8
DDR3 Address[13]
SSTL-15 Class I
DDR3_A[14]
PIN_AG12
DDR3 Address[14]
SSTL-15 Class I
DDR3_BA[0]
PIN_AH10
DDR3 Bank Address[0]
SSTL-15 Class I
DDR3_BA[1]
PIN_AJ11
DDR3 Bank Address[1]
SSTL-15 Class I
DDR3_BA[2]
PIN_AK11
DDR3 Bank Address[2]
SSTL-15 Class I
DDR3_CAS_n PIN_AH7 DDR3 Column Address Strobe SSTL-15 Class I
DDR3_CKE
PIN_AJ21
Clock Enable pin for DDR3
SSTL-15 Class I
DDR3_CK_n PIN_AA15 Clock for DDR3
DIFFERENTIAL 1.5-V
SSTL
CLASS I
DDR3_CK_p PIN_AA14 Clock p for DDR3
Differential 1.5-V SSTL
Class I
DDR3_CS_n
PIN_AB15
DDR3 Chip Select
SSTL-15 Class I
DDR3_DM[0]
PIN_AH17
DDR3 Data Mask[0]
SSTL-15 Class I
DDR3_DM[1] PIN_AG23 DDR3 Data Mask[1] SSTL-15 Class I
DDR3_DM[2]
PIN_AK23
DDR3 Data Mask[2]
SSTL-15 Class I
32
DDR3_DM[3]
PIN_AJ27
DDR3 Data Mask[3]
SSTL-15 Class I
DDR3_DQ[0]
PIN_AF18
DDR3 Data[0]
SSTL-15 Class I
DDR3_DQ[1]
PIN_AE17
DDR3 Data[1]
SSTL-15 Class I
DDR3_DQ[2]
PIN_AG16
DDR3 Data[2]
SSTL-15 Class I
DDR3_DQ[3]
PIN_AF16
DDR3 Data[3]
SSTL-15 Class I
DDR3_DQ[4]
PIN_AH20
DDR3 Data[4]
SSTL-15 Class I
DDR3_DQ[5]
PIN_AG21
DDR3 Data[5]
SSTL-15 Class I
DDR3_DQ[6]
PIN_AJ16
DDR3 Data[6]
SSTL-15 Class I
DDR3_DQ[7]
PIN_AH18
DDR3 Data[7]
SSTL-15 Class I
DDR3_DQ[8]
PIN_AK18
DDR3 Data[8]
SSTL-15 Class I
DDR3_DQ[9]
PIN_AJ17
DDR3 Data[9]
SSTL-15 Class I
DDR3_DQ[10]
PIN_AG18
DDR3 Data[10]
SSTL-15 Class I
DDR3_DQ[11]
PIN_AK19
DDR3 Data[11]
SSTL-15 Class I
DDR3_DQ[12]
PIN_AG20
DDR3 Data[12]
SSTL-15 Class I
DDR3_DQ[13]
PIN_AF19
DDR3 Data[13]
SSTL-15 Class I
DDR3_DQ[14]
PIN_AJ20
DDR3 Data[14]
SSTL-15 Class I
DDR3_DQ[15]
PIN_AH24
DDR3 Data[15]
SSTL-15 Class I
DDR3_DQ[16]
PIN_AE19
DDR3 Data[16]
SSTL-15 Class I
DDR3_DQ[17]
PIN_AE18
DDR3 Data[17]
SSTL-15 Class I
DDR3_DQ[18]
PIN_AG22
DDR3 Data[18]
SSTL-15 Class I
DDR3_DQ[19]
PIN_AK22
DDR3 Data[19]
SSTL-15 Class I
DDR3_DQ[20]
PIN_AF21
DDR3 Data[20]
SSTL-15 Class I
DDR3_DQ[21] PIN_AF20 DDR3 Data[21]
SSTL-15 Class I
DDR3_DQ[22]
PIN_AH23
DDR3 Data[22]
SSTL-15 Class I
DDR3_DQ[23]
PIN_AK24
DDR3 Data[23]
SSTL-15 Class I
DDR3_DQ[24]
PIN_AF24
DDR3 Data[24]
SSTL-15 Class I
DDR3_DQ[25]
PIN_AF23
DDR3 Data[25]
SSTL-15 Class I
DDR3_DQ[26]
PIN_AJ24
DDR3 Data[26]
SSTL-15 Class I
DDR3_DQ[27]
PIN_AK26
DDR3 Data[27]
SSTL-15 Class I
DDR3_DQ[28]
PIN_AE23
DDR3 Data[28]
SSTL-15 Class I
DDR3_DQ[29]
PIN_AE22
DDR3 Data[29]
SSTL-15 Class I
DDR3_DQ[30]
PIN_AG25
DDR3 Data[30]
SSTL-15 Class I
DDR3_DQ[31]
PIN_AK27
DDR3 Data[31]
SSTL-15 Class I
DDR3_DQS_n[0] PIN_W16 DDR3 Data Strobe n[0]
Differential 1.5-V SSTL
Class I
DDR3_DQS_n[1] PIN_W17 DDR3 Data Strobe n[1]
Differential 1.5-V SSTL
Class I
DDR3_DQS_n[2] PIN_AA18 DDR3 Data Strobe n[2]
Differential 1.5-V SSTL
Class I
DDR3_DQS_n[3] PIN_AD19 DDR3 Data Strobe n[3]
Differential 1.5-V SSTL
Class I
DDR3_DQS_p[0] PIN_V16 DDR3 Data Strobe p[0]
Differential 1.5-V SSTL
Class I
DDR3_DQS_p[1] PIN_V17 DDR3 Data Strobe p[1]
Differential 1.5-V SSTL
Class I
DDR3_DQS_p[2]
PIN_Y17
DDR3 Data Strobe p[2]
Differential 1.5-V SSTL
33
Class I
DDR3_DQS_p[3] PIN_AC20 DDR3 Data Strobe p[3]
Differential 1.5-V SSTL
Class I
DDR3_ODT
PIN_AE16
DDR3 On-die Termination
SSTL-15 Class I
DDR3_RAS_n
PIN_AH8
DDR3 Row Address Strobe
SSTL-15 Class I
DDR3_RESET_n
PIN_AK21
DDR3 Reset
SSTL-15 Class I
DDR3_WE_n
PIN_AJ6
DDR3 Write Enable
SSTL-15 Class I
DDR3_RZQ PIN_AG17
External reference ball for
output drive calibration
1.5V
3.6.7 Temperature Sensor
The board contains a temperature sensor (Analog Devices ADT7301) to monitor the ambient
temperature. It is a band gap temperature sensor with a 13-bit ADC to monitor and digitize the
temperature reading to a resolution of 0.03125°C. The interface between sensor and FPGA is SPI
serial interface. Detailed information for using the sensor is available in its datasheet, which can be
found on the manufacturer’s website, or in the Datasheets\TEMP_Sensor folder on the SoCKit
System CD. Figure 3-21 shows the connections between temperature sensor and Cyclone V SoC
FPGA. Table 3-20 gives the all the pin assignments of the sensor.
Figure 3-21 Connections between FPGA and Temperature Sensor
Table 3-20 Pin Assignments for Temperature Sensor
Signal Name FPGA Pin No. Description I/O Standard
TEMP_CS_n
PIN_AF8
Temp Sensor Chip Select Input.
3.3V
TEMP_DIN
PIN_AG7
Temp Sensor Serial Data Input
3.3V
TEMP_DOUT
PIN_AG1
Temp Sensor Serial Data Outpu
3.3V
TEMP_SCLK
PIN_AF9
Temp Sensor Serial Clock Input
3.3V
34
3
3
.
.
7
7
I
I
n
n
t
t
e
e
r
r
f
f
a
a
c
c
e
e
o
o
n
n
H
H
a
a
r
r
d
d
P
P
r
r
o
o
c
c
e
e
s
s
s
s
o
o
r
r
S
S
y
y
s
s
t
t
e
e
m
m
(
(
H
H
P
P
S
S
)
)
This section introduces the interfaces connected to the HPS section of the FPGA. Users can access these interfaces
via the HPS processor.
3
3
.
.
7
7
.
.
1
1
U
U
s
s
e
e
r
r
P
P
u
u
s
s
h
h
-
-
b
b
u
u
t
t
t
t
o
o
n
n
s
s
,
,
S
S
w
w
i
i
t
t
c
c
h
h
e
e
s
s
a
a
n
n
d
d
L
L
E
E
D
D
o
o
n
n
H
H
P
P
S
S
Like the FPGA, the HPS also features its own set of switches, buttons, LEDs, and other user
interfaces. Users can control these interfaces for observing HPS status and debugging.
Table 3-21 gives the all the pin assignments of all the user interfaces.
Table 3-21 Pin Assignments for LEDs, Switches and Buttons
Signal Name HPS GPIO Register/bit Function
HPS_KEY[0]
GPI8
GPIO2[21]
Input only
HPS_KEY[1]
GPI9
GPIO2[22]
Input only
HPS_KEY[2]
GPI10
GPIO2[23]
Input only
HPS_KEY[3]
GPI11
GPIO2[24]
Input only
HPS_SW[0]
GPI7
GPIO2[20]
Input only
HPS_SW[1]
GPI6
GPIO2[19]
Input only
HPS_SW[2]
GPI5
GPIO2[18]
Input only
HPS_SW[3]
GPI4
GPIO2[17]
Input only
HPS_LED[0]
GPIO54
GPIO1[25]
I/O
HPS_LED[1]
GPIO55
GPIO1[26]
I/O
HPS_LED[2]
GPIO56
GPIO1[27]
I/O
HPS_LED[3]
GPIO57
GPIO1[28]
I/O
3
3
.
.
7
7
.
.
2
2
G
G
i
i
g
g
a
a
b
b
i
i
t
t
E
E
t
t
h
h
e
e
r
r
n
n
e
e
t
t
The board provides Ethernet support via an external Micrel KSZ9021RN PHY chip and HPS
Ethernet MAC function. The KSZ9021RN chip with integrated 10/100/1000 Mbps Gigabit Ethernet
transceiver support RGMII MAC interfaces. Figure 3-22 shows the connection setup between the
Gigabit Ethernet PHY and Cyclone V SoC FPGA.
35
The associated pin assignments are listed in Table 3-22. For detailed information on how to use the
KSZ9021RN refers to its datasheet and application notes, which are available on the manufacturer’s
website.
Figure 3-22 Connections between Cyclone V SoC FPGA and Ethernet
Table 3-22 Pin Assignments for Ethernet PHY
Signal Name FPGA Pin No. Description I/O Standard
HPS_ENET_TX_EN
PIN_A20
GMII and MII transmit enable
3.3V
HPS_ENET_TX_DATA[0]
PIN_F20
MII transmit data[0]
3.3V
HPS_ENET_TX_DATA[1]
PIN_J19
MII transmit data[1]
3.3V
HPS_ENET_TX_DATA[2]
PIN_F21
MII transmit data[2]
3.3V
HPS_ENET_TX_DATA[3]
PIN_F19
MII transmit data[3]
3.3V
HPS_ENET_RX_DV
PIN_K17
GMII and MII receive data valid
3.3V
HPS_ENET_RX_DATA[0]
PIN_A21
GMII and MII receive data[0]
3.3V
HPS_ENET_RX_DATA[1]
PIN_B20
GMII and MII receive data[1]
3.3V
HPS_ENET_RX_DATA[2]
PIN_B18
GMII and MII receive data[2]
3.3V
HPS_ENET_RX_DATA[3]
PIN_D21
GMII and MII receive data[3]
3.3V
HPS_ENET_RX_CLK
PIN_G20
GMII and MII receive clock
3.3V
HPS_ENET_RESET_n
PIN_E18
Hardware Reset Signal
3.3V
HPS_ENET_MDIO
PIN_E21
Management Data
3.3V
HPS_ENET_MDC
PIN_B21
Management Data Clock Reference
3.3V
HPS_ENET_INT_n
PIN_C19
Interrupt Open Drain Output
3.3V
HPS_ENET_GTX_CLK
PIN_H19
GMII Transmit Clock
3.3V
36
Additionally, the Ethernet PHY (KSZ9021RNI) LED status has been set to tri-color dual LED mode.
The LED control signals are connected to LEDs (orange and green) on the RJ45 connector. States
and definitions can be found in Table 3-23, which can display the current status of the Ethernet. For
example once the green LED lights, the board has been connected to Giga bit Ethernet.
Table 3-23 Tri-Color Dual LED Mode-Pin Definition
LED (State)
LED (Definition)
Link /Activity
LED2 LED1 LED2 LED1
H
H
OFF
OFF
Link off
L
H
ON
OFF
1000 Link / No Activity
Toggle
H
Blinking
OFF
1000 Link / Activity (RX, TX)
H
L
OFF
ON
100 Link / No Activity
H
Toggle
OFF
Blinking
100 Link / Activity (RX, TX)
L
L
ON
ON
10 Link/ No Activity
Toggle
Toggle
Blinking
Blinking
10 Link / Activity (RX, TX)
3
3
.
.
7
7
.
.
3
3
U
U
A
A
R
R
T
T
The board has one UART interface connected for communication with the HPS. This interface
wouldn’t support HW flow control signals. The physical interface is done using UART-USB
onboard bridge from an FT232R chip and connects to the host using a Micro-USB (B) connector.
For detailed information on how to use the transceiver, please refer to the datasheet, which is
available on the manufacturer’s website, or in the Datasheets\FT232 folder on the SoCKit System
CD. Figure 3-23 shows the related schematics, and Table 3-24 lists the pin assignments of HPS in
Cyclone V SoC FPGA.
Figure 3-23 Connections between the Cyclone V SoC FPGA and FT232R Chip
37
Table 3-24 UART Interface I/O
Signal Name
FPGA Pin No.
Description
I/O Standard
HPS_UART_RX
PIN_B25
HPS UART Receiver
3.3V
HPS_UART_TX
PIN_C25
HPS UART Transmitter
3.3V
HPS_CONV_USB_n
PIN_B15
Reserve
3.3V
3
3
.
.
7
7
.
.
4
4
D
D
D
D
R
R
3
3
M
M
e
e
m
m
o
o
r
r
y
y
o
o
n
n
H
H
P
P
S
S
The DDR3 devices that are connected to the HPS are the exact same devices connected to the
FPGA in capacity (1GB) and data-width (32-bit), comprised of two x16 devices with a single
address/command bus. This interface connects to dedicate Hard Memory Controller for HPS I/O
banks and the target speed is 400 MHz. Table 3-25 lists DDR3 pin assignments, I/O standards and
descriptions with Cyclone V SoC FPGA.
Table 3-25 Pin Assignments for DDR3 Memory
Signal Name FPGA Pin No. Description I/O Standard
HPS_DDR3_A[0]
PIN_F26
HPS DDR3 Address[0]
SSTL-15 Class I
HPS_DDR3_A[1]
PIN_G30
HPS DDR3 Address[1]
SSTL-15 Class I
HPS_DDR3_A[2]
PIN_F28
HPS DDR3 Address[2]
SSTL-15 Class I
HPS_DDR3_A[3]
PIN_F30
HPS DDR3 Address[3]
SSTL-15 Class I
HPS_DDR3_A[4]
PIN_J25
HPS DDR3 Address[4]
SSTL-15 Class I
HPS_DDR3_A[5]
PIN_J27
HPS DDR3 Address[5]
SSTL-15 Class I
HPS_DDR3_A[6]
PIN_F29
HPS DDR3 Address[6]
SSTL-15 Class I
HPS_DDR3_A[7]
PIN_E28
HPS DDR3 Address[7]
SSTL-15 Class I
HPS_DDR3_A[8]
PIN_H27
HPS DDR3 Address[8]
SSTL-15 Class I
HPS_DDR3_A[9]
PIN_G26
HPS DDR3 Address[9]
SSTL-15 Class I
HPS_DDR3_A[10]
PIN_D29
HPS DDR3 Address[10]
SSTL-15 Class I
HPS_DDR3_A[11]
PIN_C30
HPS DDR3 Address[11]
SSTL-15 Class I
HPS_DDR3_A[12]
PIN_B30
HPS DDR3 Address[12]
SSTL-15 Class I
HPS_DDR3_A[13]
PIN_C29
HPS DDR3 Address[13]
SSTL-15 Class I
HPS_DDR3_A[14]
PIN_H25
HPS DDR3 Address[14]
SSTL-15 Class I
HPS_DDR3_BA[0]
PIN_E29
HPS DDR3 Bank Address[0]
SSTL-15 Class I
HPS_DDR3_BA[1]
PIN_J24
HPS DDR3 Bank Address[1]
SSTL-15 Class I
HPS_DDR3_BA[2]
PIN_J23
HPS DDR3 Bank Address[2]
SSTL-15 Class I
HPS_DDR3_CAS_n
PIN_E27
DDR3 Column Address Strobe
SSTL-15 Class I
HPS_DDR3_CKE
PIN_L29
HPS DDR3 Clock Enable
SSTL-15 Class I
HPS_DDR3_CK_n
PIN_L23
HPS DDR3 Clock
Differential 1.5-V SSTL Class I
HPS_DDR3_CK_p
PIN_M23
HPS DDR3 Clock p
Differential 1.5-V SSTL Class I
HPS_DDR3_CS_n
PIN_H24
HPS DDR3 Chip Select
SSTL-15 Class I
HPS_DDR3_DM[0]
PIN_K28
HPS DDR3 Data Mask[0]
SSTL-15 Class I
HPS_DDR3_DM[1]
PIN_M28
HPS DDR3 Data Mask[1]
SSTL-15 Class I
HPS_DDR3_DM[2]
PIN_R28
HPS DDR3 Data Mask[2]
SSTL-15 Class I
HPS_DDR3_DM[3]
PIN_W30
HPS DDR3 Data Mask[3]
SSTL-15 Class I
38
HPS_DDR3_DQ[0]
PIN_K23
HPS DDR3 Data[0]
SSTL-15 Class I
HPS_DDR3_DQ[1]
PIN_K22
HPS DDR3 Data[1]
SSTL-15 Class I
HPS_DDR3_DQ[2]
PIN_H30
HPS DDR3 Data[2]
SSTL-15 Class I
HPS_DDR3_DQ[3]
PIN_G28
HPS DDR3 Data[3]
SSTL-15 Class I
HPS_DDR3_DQ[4]
PIN_L25
HPS DDR3 Data[4]
SSTL-15 Class I
HPS_DDR3_DQ[5]
PIN_L24
HPS DDR3 Data[5]
SSTL-15 Class I
HPS_DDR3_DQ[6]
PIN_J30
HPS DDR3 Data[6]
SSTL-15 Class I
HPS_DDR3_DQ[7]
PIN_J29
HPS DDR3 Data[7]
SSTL-15 Class I
HPS_DDR3_DQ[8]
PIN_K26
HPS DDR3 Data[8]
SSTL-15 Class I
HPS_DDR3_DQ[9]
PIN_L26
HPS DDR3 Data[9]
SSTL-15 Class I
HPS_DDR3_DQ[10]
PIN_K29
HPS DDR3 Data[10]
SSTL-15 Class I
HPS_DDR3_DQ[11]
PIN_K27
HPS DDR3 Data[11]
SSTL-15 Class I
HPS_DDR3_DQ[12]
PIN_M26
HPS DDR3 Data[12]
SSTL-15 Class I
HPS_DDR3_DQ[13]
PIN_M27
HPS DDR3 Data[13]
SSTL-15 Class I
HPS_DDR3_DQ[14]
PIN_L28
HPS DDR3 Data[14]
SSTL-15 Class I
HPS_DDR3_DQ[15]
PIN_M30
HPS DDR3 Data[15]
SSTL-15 Class I
HPS_DDR3_DQ[16]
PIN_U26
HPS DDR3 Data[16]
SSTL-15 Class I
HPS_DDR3_DQ[17]
PIN_T26
HPS DDR3 Data[17]
SSTL-15 Class I
HPS_DDR3_DQ[18]
PIN_N29
HPS DDR3 Data[18]
SSTL-15 Class I
HPS_DDR3_DQ[19]
PIN_N28
HPS DDR3 Data[19]
SSTL-15 Class I
HPS_DDR3_DQ[20]
PIN_P26
HPS DDR3 Data[20]
SSTL-15 Class I
HPS_DDR3_DQ[21]
PIN_P27
HPS DDR3 Data[21]
SSTL-15 Class I
HPS_DDR3_DQ[22]
PIN_N27
HPS DDR3 Data[22]
SSTL-15 Class I
HPS_DDR3_DQ[23]
PIN_R29
HPS DDR3 Data[23]
SSTL-15 Class I
HPS_DDR3_DQ[24]
PIN_P24
HPS DDR3 Data[24]
SSTL-15 Class I
HPS_DDR3_DQ[25]
PIN_P25
HPS DDR3 Data[25]
SSTL-15 Class I
HPS_DDR3_DQ[26]
PIN_T29
HPS DDR3 Data[26]
SSTL-15 Class I
HPS_DDR3_DQ[27]
PIN_T28
HPS DDR3 Data[27]
SSTL-15 Class I
HPS_DDR3_DQ[28]
PIN_R27
HPS DDR3 Data[28]
SSTL-15 Class I
HPS_DDR3_DQ[29]
PIN_R26
HPS DDR3 Data[29]
SSTL-15 Class I
HPS_DDR3_DQ[30]
PIN_V30
HPS DDR3 Data[30]
SSTL-15 Class I
HPS_DDR3_DQ[31]
PIN_W29
HPS DDR3 Data[31]
SSTL-15 Class I
HPS_DDR3_DQS_n[0]
PIN_M19
HPS DDR3 Data Strobe n[0]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_n[1]
PIN_N24
HPS DDR3 Data Strobe n[1]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_n[2]
PIN_R18
HPS DDR3 Data Strobe n[2]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_n[3]
PIN_R21
HPS DDR3 Data Strobe n[3]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_p[0]
PIN_N18
HPS DDR3 Data Strobe p[0]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_p[1]
PIN_N25
HPS DDR3 Data Strobe p[1]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_p[2]
PIN_R19
HPS DDR3 Data Strobe p[2]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_p[3]
PIN_R22
HPS DDR3 Data Strobe p[3]
Differential 1.5-V SSTL Class I
HPS_DDR3_ODT
PIN_H28
HPS DDR3 On-die Termination
SSTL-15 Class I
HPS_DDR3_RAS_n
PIN_D30
DDR3 Row Address Strobe
SSTL-15 Class I
HPS_DDR3_RESET_n
PIN_P30
HPS DDR3 Reset
SSTL-15 Class I
HPS_DDR3_WE_n
PIN_C28
HPS DDR3 Write Enable
SSTL-15 Class I
HPS_DDR3_RZQ PIN_D27 External reference ball for
output drive calibration
1.5 V
39
3
3
.
.
7
7
.
.
5
5
Q
Q
S
S
P
P
I
I
F
F
l
l
a
a
s
s
h
h
The board supports a 1G-bit serial NOR flash device for non-volatile storage of HPS boot code,
user data and program. The device is connected to HPS dedicated interface. It may contain
secondary boot code.
This device has a 4-bit data interface and uses 3.3V CMOS signaling standard. Connections
between Cyclone V SoC FPGA and Flash are shown in Figure 3-24.
To program the QSPI flash, the HPS Flash Programmer is provided both as part of the Altera
Quartus II suite and as part of the free Altera Quartus II Programmer. The HPS Flash Programmer
sends file contents over an Altera download cable, such as the USB Blaster II, to the HPS, and
instructs the HPS to write the data to the flash memory.
Figure 3-24 Connections Between Cyclone V SoC FPGA and QSPI Flash
Table 3-26 below summarizes the pins on the flash device. Signal names are from the device datasheet and
directions are relative to the Cyclone V SoC FPGA.
Table 3-26 QSPI Flash Interface I/O
Signal Name
FPGA Pin No.
Description
I/O Standard
HPS_FLASH_DATA[0] PIN_C20 HPS FLASH Data[0] 3.3V
HPS_FLASH_DATA[1]
PIN_H18
HPS FLASH Data[1]
3.3V
HPS_FLASH_DATA[2]
PIN_A19
HPS FLASH Data[2]
3.3V
HPS_FLASH_DATA[3]
PIN_E19
HPS FLASH Data[3]
3.3V
HPS_FLASH_DCLK
PIN_D19
HPS FLASH Data Clock
3.3V
HPS_FLASH_NCSO
PIN_A18
HPS FLASH Chip Enable
3.3V
40
3
3
.
.
7
7
.
.
6
6
M
M
i
i
c
c
r
r
o
o
S
S
D
D
The board supports Micro SD card interface using x4 data lines. And it may contain secondary boot
code for HPS. Figure 3-25 shows the related signals.
Finally, Table 3-27 lists all the associated pins for interfacing HPS respectively.
Figure 3-25 Connections between Cyclone V SoC FPGA and SD Card Socket
Table 3-27 SD Card Socket Pin Assignments
Signal Name FPGA Pin No. Description I/O Standard
HPS_SD_CLK
PIN_A16
HPS SD Clock
3.3V
HPS_SD_CMD
PIN_F18
HPS SD Command Line
3.3V
HPS_SD_DATA[0]
PIN_G18
HPS SD Data[0]
3.3V
HPS_SD_DATA[1]
PIN_C17
HPS SD Data[1]
3.3V
HPS_SD_DATA[2]
PIN_D17
HPS SD Data[2]
3.3V
HPS_SD_DATA[3]
PIN_B16
HPS SD Data[3]
3.3V
3
3
.
.
7
7
.
.
7
7
U
U
S
S
B
B
2
2
.
.
0
0
O
O
T
T
G
G
P
P
H
H
Y
Y
The board provides USB interfaces using the SMSC USB3300 controller. A SMSC USB3300
device in a 32-pin QFN package device is used to interface to a single Type AB Micro-USB
connector. This device supports UTMI+ Low Pin Interface (ULPI) to communicate to USB 2.0
controller in HPS. As defined by OTG mode, the PHY can operate in Host or Device modes. When
operating in Host mode, the interface will supply the power to the device through the Micro-USB
interface. Figure 3-26 shows the schematic diagram of the USB circuitry; the pin assignments for
the associated interface are listed in Table 3-28.
41
Figure 3-26 Connections between Cyclone V SoC FPGA and USB OTG PHY
Table 3-28 USB OTG PHY Pin Assignments
Signal Name
FPGA Pin No.
Description
I/O Standard
HPS_USB_CLKOUT
PIN_N16
60MHz Reference Clock Output
3.3V
HPS_USB_DATA[0]
PIN_E16
HPS USB_DATA[0]
3.3V
HPS_USB_DATA[1]
PIN_G16
HPS USB_DATA[1]
3.3V
HPS_USB_DATA[2]
PIN_D16
HPS USB_DATA[2]
3.3V
HPS_USB_DATA[3]
PIN_D14
HPS USB_DATA[3]
3.3V
HPS_USB_DATA[4]
PIN_A15
HPS USB_DATA[4]
3.3V
HPS_USB_DATA[5]
PIN_C14
HPS USB_DATA[5]
3.3V
HPS_USB_DATA[6]
PIN_D15
HPS USB_DATA[6]
3.3V
HPS_USB_DATA[7]
PIN_M17
HPS USB_DATA[7]
3.3V
HPS_USB_DIR
PIN_E14
Direction of the Data Bus
3.3V
HPS_USB_NXT
PIN_A14
Throttle the Data
3.3V
HPS_USB_RESET_PHY
PIN_G17
HPS USB PHY Reset
3.3V
HPS_USB_STP
PIN_C15
Stop Data Stream on theBus
3.3V
3
3
.
.
7
7
.
.
8
8
G
G
-
-
S
S
e
e
n
n
s
s
o
o
r
r
The board is equipped with a digital accelerometer sensor module. The ADXL345 is a small, thin,
ultralow power assumption 3-axis accelerometer with high-resolution measurement. Digitalized
output is formatted as 16-bit twos complement and can be accessed using I2C interface. Connected
to the I2C interface includes two peripherals, the G-sensor and the LTC connector. The I2C address
of the G-Sensor device is 0xA6/0xA7. For more detailed information of better using this chip,
please refer to its datasheet which is available on manufacturer’s website or under the Datasheet
folder of the SoCKit System CD. Figure 3-27 shows the connections between ADXL345 and HPS.
The associated pin assignments are listed in Table 3-29.
42
Figure 3-27 Connections between Cyclone V SoC FPGA and G-Sensor
Table 3-29 G-Sensor Pin Assignments
Signal Name
FPGA Pin No.
Description
I/O Standard
HPS_GSENSOR_INT
PIN_B22
HPS GSENSOR Interrupt Output
3.3V
HPS_I2C_CLK
PIN_H23
HPS I2C Clock (share bus with LTC)
3.3V
HPS_I2C_SDA
PIN_A25
HPS I2C Data (share bus)
3.3V
3
3
.
.
7
7
.
.
9
9
1
1
2
2
8
8
x
x
6
6
4
4
D
D
o
o
t
t
s
s
L
L
C
C
D
D
The board equips an LCD Module with 128x64 dots for display capabilities. The LCD module uses
serial peripheral interface to connect with the HPS. To use the LCD module, please refer to the
datasheet folder in SoCKit System CD. Figure 3-28 shows the connections between the HPS and
LCD module. The default setting for LCD backlight power is ON by shorting the pins of header JP1.
Table 3-30 lists the pin assignments between LCD module and Cyclone V SoC FPGA.
43
Figure 3-28 Connections between Cyclone V SoC FPGA and LCD Module
Table 3-30 LCD Module Pin Assignments
Signal Name FPGA Pin No. Description I/O Standard
HPS_LCM_D_C
PIN_G22
HPS LCM Data bit is Data/Command
3.3V
HPS_LCM_RST_N
PIN_B26
HPS LCM Reset
3.3V
HPS_LCM_SPIM_CLK
PIN_C23
SPI Clock
3.3V
HPS_LCM_SPIM_MOSI
PIN_D22
SPI Master Output /Slave Input
3.3V
HPS_LCM_SPIM_SS
PIN_D24
SPI Slave Select
3.3V
3
3
.
.
7
7
.
.
1
1
0
0
L
L
T
T
C
C
C
C
o
o
n
n
n
n
e
e
c
c
t
t
o
o
r
r
The board allows connection to interface card from Linear Technology. The interface is
implemented using 14-pin header that can be connected to variety of demo boards from Linear
Technology. It will be connected to SPI Master and I2C ports of the HPS to allow bidirectional
communication with two types of protocols. The 14-pin header will allow for GPIO, SPI and I2C
extension for user purposes if the interfaces to Linear Technology board aren’t in use. Connections
between the LTC connector and the HPS are shown in Figure 3-29, and the functions of the 14 pins
is listed in Table 3-31.
44
Figure 3-29 Connections between the LTC Connector and HPS
Table 3-31 LTC Connector Pin Assignments
Signal Name FPGA Pin No. Description I/O Standard
HPS_LTC_GPIO
PIN_F16
HPS LTC GPIO
3.3V
HPS_I2C_CLK PIN_H23 HPS I2C Clock (share bus with
G-Sensor)
3.3V
HPS_I2C_SDA
PIN_A25
HPS I2C Data (share bus with G-Sensor)
3.3V
HPS_SPIM_CLK
PIN_A23
SPI Clock
3.3V
HPS_SPIM_MISO
PIN_B23
SPI Master Input/Slave Output
3.3V
HPS_SPIM_MOSI
PIN_C22
SPI Master Output /Slave Input
3.3V
HPS_SPIM_SS
PIN_H20
SPI Slave Select
3.3V
45
Chapter 4
SoCKit System Builder
This chapter describes how users can create a custom design project on the board by using the
SoCKit Software Tool – SoCKit System Builder.
4
4
.
.
1
1
I
I
n
n
t
t
r
r
o
o
d
d
u
u
c
c
t
t
i
i
o
o
n
n
The SoCKit System Builder is a Windows-based software utility, designed to assist users to create a
Quartus II project for the board within minutes. The generated Quartus II project files include:
• Quartus II Project File (.qpf)
• Quartus II Setting File (.qsf)
• Top-Level Design File (.v)
• Synopsis Design Constraints file (.sdc)
• Pin Assignment Document (.htm)
By providing the above files, the SoCKit System Builder prevents occurrence of situations that are
prone to errors when users manually edit the top-level design file or place pin assignments. The
common mistakes that users encounter are the following:
1. Board damage due to wrong pin/bank voltage assignments.
2. Board malfunction caused by wrong device connections or missing pin counts for connected
ends.
3. Performance degeneration due to improper pin assignments.
4
4
.
.
2
2
G
G
e
e
n
n
e
e
r
r
a
a
l
l
D
D
e
e
s
s
i
i
g
g
n
n
F
F
l
l
o
o
w
w
This section will introduce the general design flow to build a project for the development board via
the SoCKit System Builder. The general design flow is illustrated in Figure 4-1.
Users should launch the SoCKit System Builder and create a new project according to their design
requirements. When users complete the settings, the SoCKit System Builder will generate two
major files, a top-level design file (.v) and a Quartus II setting file (.qsf).
46
The top-level design file contains top-level Verilog HDL wrapper for users to add their own
design/logic. The Quartus II setting file contains information such as FPGA device type, top-level
pin assignment, and the I/O standard for each user-defined I/O pin.
Finally, the Quartus II programmer must be used to download SOF file to the development board
using a JTAG interface.
Figure 4-1 The general design flow of building a design
4
4
.
.
3
3
U
U
s
s
i
i
n
n
g
g
S
S
o
o
C
C
K
K
i
i
t
t
S
S
y
y
s
s
t
t
e
e
m
m
B
B
u
u
i
i
l
l
d
d
e
e
r
r
This section provides the detailed procedures on how the SoCKit System Builder is used.
Install and launch the SoCKit System Builder
The SoCKit System Builder is located in the directory:
“Tools\SOC_Kit_system_builder” on the SoCKit System CD. Users can copy the whole folder to a
host computer without installing the utility. Launch the SoCKit System Builder by executing the
SOC_Kit_SystemBuilder.exe on the host computer and the GUI window will appear as shown in
Figure 4-2.
48
Figure 4-3 Board Type and Project Name
System Configuration
Under the System Configuration users are given the flexibility of enabling their choice of included
components on the board as shown in Figure 4-4. Each component of the board is listed where
users can enable or disable a component according to their design by simply marking a check or
removing the check in the field provided. If the component is enabled, the SoCKit System Builder
will automatically generate the associated pin assignments including the pin name, pin location, pin
direction, and I/O standard.
49
Figure 4-4 System Configuration Group
HSMC Expansion
Users can connect HSMC daughter cards onto the HSMC connector located on the development
board shown in Figure 4-5. Select the daughter card you wish to add to your design under the
appropriate HSMC connector to which the daughter card is connected. The System Builder will
automatically generate the associated pin assignment including pin name, pin location, pin direction,
and I/O standard.
50
Figure 4-5 HSMC Expansion Group
The “Prefix Name” is an optional feature that denotes the pin name of the daughter card assigned in
your design. Users may leave this field empty.
Project Setting Management
The SoCKit System Builder also provides functions to restore default setting, loading a setting, and
saving users’ board configuration file shown in Figure 4-6. Users can save the current board
configuration information into a .cfg file and load it to the SoCKit System Builder.
51
Figure 4-6 Project Settings
Project Generation
When users press the Generate button, the SoCKit System Builder will generate the corresponding
Quartus II files and documents as listed in the Table 4-1:
Table 4-1 The files generated by SoCKit System Builder
No.
Filename
Description
1 <Project name>.v Top level Verilog HDL file for Quartus II
2 <Project name>.qpf Quartus II Project File
3 <Project name>.qsf Quartus II Setting File
4 <Project name>.sdc Synopsis Design Constraints file for Quartus II
5 <Project name>.htm Pin Assignment Document
Users can use Quartus II software to add custom logic into the project and compile the project to
generate the SRAM Object File (.sof).
52
Chapter 5
Examples For FPGA
This chapter provides a number of examples of advanced circuits implemented by RTL or Qsys on
the SoCKit board. These circuits provide demonstrations of the major features which connected to
FPGA interface on the board, such as audio, DDR3 and IR receiver. All of the associated files can
be found in the Demonstrations/FPGA folder on the SoCKit System CD.
Installing the Demonstrations
To install the demonstrations on your computer:
Copy the directory Demonstrations into a local directory of your choice. It is important to ensure
that the path to your local directory contains no spaces – otherwise, the Nios II software will not
work. Note Quartus II v13 is required for all SoCKit demonstrations to support Cyclone V SoC
device.
5
5
.
.
1
1
A
A
u
u
d
d
i
i
o
o
R
R
e
e
c
c
o
o
r
r
d
d
i
i
n
n
g
g
a
a
n
n
d
d
P
P
l
l
a
a
y
y
i
i
n
n
g
g
This demonstration shows how to implement an audio recorder and player using the SoCKit board
with the built-in Audio CODEC chip. This demonstration is developed based on Qsys and Eclipse.
Figure 5-1 shows the man-machine interface of this demonstration. Two push-buttons and four
slide switches are used for users to configure this audio system: SW0 is used to specify recording
source to be Line-in or MIC-In. SW1, SW2, and SW3 are used to specify recording sample rate as
96K, 48K, 44.1K, 32K, or 8K. Table 5-1 and
Table 5-2 summarize the usage of Slide switches for configuring the audio recorder and player.
53
Figure 5-1 Man-Machine Interface of Audio Recorder and Player
Figure 5-2 shows the block diagram of the Audio Recorder and Player design. There are hardware
and software parts in the block diagram. The software part stores the Nios II program in the on-chip
memory. The software part is built by Eclipse in C programming language. The hardware part is
built by Qsys under Quartus II. The hardware part includes all the other blocks. The “AUDIO
Controller” is a user-defined Qsys component. It is designed to send audio data to the audio chip or
receive audio data from the audio chip.
The audio chip is programmed through I2C protocol which is implemented in C code. The I2C pins
from audio chip are connected to Qsys System Interconnect Fabric through PIO controllers. In this
example, the audio chip is configured in Master Mode. The audio interface is configured as I2S and
16-bit mode. 18.432MHz clock generated by the PLL is connected to the MCLK/XTI pin of the
audio chip through the AUDIO Controller.
54
Figure 5-2 Block diagram of the audio recorder and player
Demonstration Setup, File Locations, and Instructions
• Hardware Project directory: SoCKit _Audio
• Bit stream used: SoCKit _Audio.sof
• Software Project directory: SoCKit _Audio\software
• Connect an Audio Source to the LINE-IN port of the SoCKit board.
• Connect a Microphone to MIC-IN port on the SoCKit board.
• Connect a speaker or headset to LINE-OUT port on the SoCKit board.
• Load the bit stream into FPGA. (note *1)
• Load the Software Execution File into FPGA. (note *1)
• Configure audio with the Slide switches SW0 as shown in Table 5-1.
• Press KEY3 on the SoCKit board to start/stop audio recording (note *2)
• Press KEY2 on the SoCKit board to start/stop audio playing (note *3)
Table 5-1 Slide switches usage for audio source
Slide Switches
0 – DOWN Position
1 – UP Position
SW0
Audio is from MIC
Audio is from LINE-IN
55
Table 5-2 Slide switch setting for sample rate switching for audio recorder and player
SW3
(0 – DOWN;
1- UP)
SW2
(0 – DOWN;
1-UP)
SW1
(0 – DOWN;
1-UP)
Sample Rate
0
0
0
96K
0
0
1
48K
0
1
0
44.1K
0
1
1
32K
1
0
0
8K
Unlisted combination
96K
Note:
(1). Execute SoCKit _Audio \demo_batch\ SoCKit _Audio.bat will download .sof and .elf files.
(2). Recording process will stop if audio buffer is full.
(3). Playing process will stop if audio data is played completely.
5
5
.
.
2
2
A
A
K
K
a
a
r
r
a
a
o
o
k
k
e
e
M
M
a
a
c
c
h
h
i
i
n
n
e
e
This demonstration uses the microphone-in, line-in, and line-out ports on the SOCKIT board to
create a Karaoke Machine application. The SSM2603 audio CODEC is configured in the master
mode, with which the audio CODEC generates AD/DA serial bit clock (BCK) and the left/right
channel clock (LRCK) automatically. As indicated in Figure 5-3, the I2C interface is used to
configure the Audio CODEC. The sample rate and gain of the CODEC are set in this manner, and
the data input from the line-in port is then mixed with the microphone-in port and the result is sent
to the line-out port.
For this demonstration the sample rate is set to 48kHz. Pressing the pushbutton KEY0 reconfigures
the gain of the audio CODEC via I2C bus, cycling within ten predefined gain values (volume levels)
provided by the device.
56
Figure 5-3 Block diagram of the Karaoke Machine demonstration
Demonstration Setup, File Locations, and Instructions
• Project directory: SOCKIT_i2sound
• Bit stream used: SOCKIT_i2sound.sof
• Connect a microphone to the microphone-in port (pink color) on the SOCKIT board
• Connect the audio output of a music-player, such as an MP3 player or computer, to the line-in
port (blue color) on the SOCKIT board
• Connect a headset/speaker to the line-out port (green color) on the SOCKIT board
• Load the bit stream into the FPGA by execute the batch file ‘SOCKIT_i2sound’ under the
SOCKIT_i2sound\demo_batch folder
• You should be able to hear a mixture of the microphone sound and the sound from the music
player
• Press KEY0 to adjust the volume; it cycles between volume levels 0 to 9
Figure 5-4 illustrates the setup for this demonstration.
57
Figure 5-4 Setup for the Karaoke Machine
58
5
5
.
.
3
3
D
D
D
D
R
R
3
3
S
S
D
D
R
R
A
A
M
M
T
T
e
e
s
s
t
t
This demonstration presents a memory test function on the bank of DDR3-SDRAM on the SoCKit
board. The memory size of the DDR3 SDRAM bank is 1GB.
Function Block Diagram
Figure 5-5 shows the function block diagram of this demonstration. The controller uses 50 MHz as
a reference clock, generates one 300 MHz clock as memory clock, and generates one half-rate
system clock 150MHz for the controller itself.
Figure 5-5 Block Diagram of the DDR3 SDRAM (1G) Demonstration
RW_test modules read and write the entire memory space of the DDR3 through the Avalon
interface of the controller. In this project, the Avalon bus read/write test module will first write the
entire memory and then compare the read back data with the regenerated data (the same sequence as
the write data). KEY0 will trigger test control signals for the DDR3, and the LEDs will indicate the
test results according to Table 5-3.
Altera DDR3 SDRAM Controller with UniPHY
To use the Altera DDR3 controller, users need to perform three major steps:
1. Create correct pin assignments for the DDR3.
2. Setup correct parameters in DDR3 controller dialog.
3. Perform “Analysis and Synthesis” by selecting from the Quartus II menu:
ProcessStartStart Analysis & Synthesis.
4. Run the TCL files generated by DDR3 IP by selecting from the Quartus II menu:
ToolsTCL Scripts…
59
Design Tools
• 64-Bit Quartus 13.0
Demonstration Source Code
• Project directory: SoCKit_DDR3_RTL_Test
• Bit stream used: SoCKit_DDR3_RTL_Test.sof
Demonstration Batch File
Demo Batch File Folder: SoCKit_DDR3_RTL_Test \demo_batch
The demo batch file includes following files:
• Batch File: SoCKit_DDR3_RTL_Test.bat
• FPGA Configure File: SoCKit_DDR3_RTL_Test.sof
Demonstration Setup
• Make sure Quartus II is installed on your PC.
• Connect the USB cable to the USB Blaster II connector (J2) on the SoCKit board and host PC.
• Power on the SoCKit board.
• Execute the demo batch file “SoCKit_DDR3_RTL_Test.bat” under the batch file folder,
SoCKit_DDR3_RTL_Test \demo_batch.
• Press KEY0 on the SoCKit board to start the verification process. When KEY0 is pressed, the
LEDs (LED [2:0]) should turn on. At the instant of releasing KEY0, LED1, LED2 should start
blinking. After approximately 13 seconds, LED1 should stop blinking and stay on to indicate
that the DDR3 has passed the test, respectively. Table 4-2 lists the LED indicators.
• If LED2 is not blinking, it means the 50MHz clock source is not working.
• If LED1 do not start blinking after releasing KEY0, it indicates local_init_done or
local_cal_success of the corresponding DDR3 failed.
• If LED1 fail to remain on after 13 seconds, the corresponding DDR3 test has failed.
• Press KEY0 again to regenerate the test control signals for a repeat test.
Table 5-3 LED Indicators
NAME
Description
LED0
Reset
LED1 If light, DDR3 test pass
LED2 Blinks
60
5
5
.
.
4
4
D
D
D
D
R
R
3
3
S
S
D
D
R
R
A
A
M
M
T
T
e
e
s
s
t
t
b
b
y
y
N
N
i
i
o
o
s
s
I
I
I
I
Many applications use a high performance RAM, such as a DDR3 SDRAM, to provide temporary
storage. In this demonstration hardware and software designs are provided to illustrate how to
perform DDR3 memory access in QSYS. We describe how the Altera’s “DDR3 SDRAM Controller
with UniPHY” IP is used to access a DDR3-SDRAM, and how the Nios II processor is used to read
and write the SDRAM for hardware verification. The DDR3 SDRAM controller handles the
complex aspects of using DDR3 SDRAM by initializing the memory devices, managing SDRAM
banks, and keeping the devices refreshed at appropriate intervals.
System Block Diagram
Figure 5-6 shows the system block diagram of this demonstration. The system requires a 50 MHz
clock provided from the board. The DDR3 controller is configured as a 1 GB DDR3-300 controller.
The DDR3 IP generates one 300 MHz clock as SDRAM’s data clock and one half-rate system clock
150 MHz for those host controllers, e.g. Nios II processor, accessing the SDRAM. In the QSYS,
Nios II and the On-Chip Memory are designed running with the 100MHz clock, and the Nios II
program is running in the on-chip memory.
Figure 5-6 Block diagram of the DDR3 Basic Demonstration
The system flow is controlled by a Nios II program. First, the Nios II program writes test patterns
into the whole 1 GB of SDRAM. Then, it calls Nios II system function, alt_dache_flush_all, to
make sure all data has been written to SDRAM. Finally, it reads data from SDRAM for data
verification. The program will show progress in JTAG-Terminal when writing/reading data to/from
the SDRAM. When verification process is completed, the result is displayed in the JTAG-Terminal.
61
Altera DDR3 SDRAM Controller with UniPHY
To use Altera DDR3 controller, users need to perform the four major steps:
1. Create correct pin assignments for DDR3.
2. Setup correct parameters in DDR3 controller dialog.
3. Perform “Analysis and Synthesis” by clicking Quartus menu: ProcessStartStart
Analysis & Synthesis.
4. Run the TCL files generated by DDR3 IP by clicking Quartus menu: ToolsTCL Scripts…
Design Tools
• Quartus II 13.0
• Nios II Eclipse 13.0
Demonstration Source Code
• Quartus Project directory: SoCKit_DDR3_Nios_Test
• Nios II Eclipse: SoCKit_DDR3_Nios_Test\Software
Nios II Project Compilation
Before you attempt to compile the reference design under Nios II Eclipse, make sure the project is
cleaned first by clicking ‘Clean’ from the ‘Project’ menu of Nios II Eclipse.
Demonstration Batch File
Demo Batch File Folder:
SoCKit_DDR3_Nios_Test\demo_batch
The demo batch file includes following files:
• Batch File for USB-Blaster (II) : SoCKit_DDR3_Nios_Test.bat,
SoCKit_DDR3_Nios_Test_bashrc
• FPGA Configure File : SoCKit_DDR3_Nios_Test.sof
• Nios II Program: SoCKit_DDR3_Nios_Test.elf
Demonstration Setup
• Make sure Quartus II and Nios II are installed on your PC.
• Power on the SoCKit board.
• Use USB cable to connect PC and the SoCKit board (J2) and install USB Blaster driver if
necessary.
62
• Execute the demo batch file “SoCKit_DDR3_Nios_Test.bat” for USB-Blaster II under the batch
file folder, SoCKit_DDR3_Nios_Test\demo_batch
• After Nios II program is downloaded and executed successfully, a prompt message will be
displayed in nios2-terminal.
• Press Button3~KEY0 of the SoCKit board to start SDRAM verify process. Press KEY0 for
continued test and press any to terminate the continued test.
• The program will display progressing and result information, as shown in Figure 5-7.
Figure 5-7 Display Progress and Result Information for the DDR3 Demonstration
5
5
.
.
5
5
I
I
R
R
R
R
e
e
c
c
e
e
i
i
v
v
e
e
r
r
D
D
e
e
m
m
o
o
n
n
s
s
t
t
r
r
a
a
t
t
i
i
o
o
n
n
In this demonstration, the key code information that the user has pressed on the remote
controller(Figure 5-8，Table 5-4) will be displayed in nios2-terminal. The remote controller can be
purchased from Terasic website or user can use any remote control which the IR carrier frequency is
38K HZ. The following descriptions of this demonstration are used Terasic remote controller. Users
only need to point the remote controller to the IR receiver on SoCKit and press the key. After the
signal being decoded and processed through FPGA, the related information will be included in
hexadecimal format, which contains Custom Code, Key Code and Inversed Key Code. The Custom
Code and Key Code are used to identify a remote controller and key on the remote controller,
respectively. At final, the key code information will be displayed in nios2-terminal. Figure 5-9
shows the block diagram of the design.
63
Figure 5-8 Terasic Remote controller
Table 5-4 Key code information for each Key on remote controller
Key Key Code Key Key Code Key Key Code Key Key Code
0x0F
0x13
0x10
0x12
0x01
0x02
0x03
0x1A
0x04
0x05
0x06
0x1E
0x07
0x08
0x09
0x1B
0x11
0x00
0x17
0x1F
0x16
0x14
0x18
0x0C
64
Figure 5-9 Block Diagram of the IR Receiver Demonstration
Next we will introduce how this information being decoded and then displayed in this demo.
When a key on the remote controller is pressed, the remote controller will emit a standard frame,
shown in Figure 5-10. The beginning of the frame is the lead code represents the start bit, and then
is the key-related information, and the last 1 bit end code represents the end of the frame.
Lead Code 1bit Custom Code 16bits Key Code 8bits
Inv Key Code
8bits
End
Code
1bit
Figure 5-10 The transmitting frame of the IR remote controller
65
After the IR receiver on SoCKit receives this frame, it will directly transmit that to FPGA. In this
demo, the IP of IR receiver controller is implemented in the FPGA. As Figure 5-11 shows, it
includes Code Detector, State Machine, and Shift Register. First, the IR receiver demodulates the
signal inputs to Code Detector block .The Code Detector block will check the Lead Code and
feedback the examination result to State Machine block.
The State Machine block will change the state from IDLE to GUIDANCE once the Lead code is
detected. Once the Code Detector has detected the Custom Code status, the current state will change
from GUIDANCE to DATAREAD state. At this state, the Code Detector will save the Custom Code
and Key/Inv Key Code and output to Shift Register then displays it in nios2-terminal. Figure 5-12
shows the state shift diagram of State Machine block. Note that the input clock should be 50MHz.
Figure 5-11 The IR Receiver controller
Figure 5-12 State shift diagram of State Machine
We can apply the IR receiver to many applications, such as integrating to the SD Card Demo, and
you can also develop other related interesting applications with it.
66
D
D
e
e
m
m
o
o
n
n
s
s
t
t
r
r
a
a
t
t
i
i
o
o
n
n
S
S
o
o
u
u
r
r
c
c
e
e
C
C
o
o
d
d
e
e
• Project directory: SoCKit_IR
• Bit stream used: SoCKit_IR.sof
• Nios II Workspace: SoCKit_IR\Software
D
D
e
e
m
m
o
o
n
n
s
s
t
t
r
r
a
a
t
t
i
i
o
o
n
n
B
B
a
a
t
t
c
c
h
h
F
F
i
i
l
l
e
e
Demo Batch File Folder: SoCKit_IR\demo_batch
The demo batch file includes the following files:
• Batch File: SoCKit_IR.bat, SoCKit_IR_bashrc
• FPGA Configure File : SoCKit_IR.sof
• Nios II Program: SoCKit_IR.elf
D
D
e
e
m
m
o
o
n
n
s
s
t
t
r
r
a
a
t
t
i
i
o
o
n
n
S
S
e
e
t
t
u
u
p
p
,
,
F
F
i
i
l
l
e
e
L
L
o
o
c
c
a
a
t
t
i
i
o
o
n
n
s
s
,
,
a
a
n
n
d
d
I
I
n
n
s
s
t
t
r
r
u
u
c
c
t
t
i
i
o
o
n
n
s
s
• Make sure Quartus II and Nios II are installed on your PC.
• Power on the SoCKit board.
• Connect USB Blaster to the SoCKit board and install USB Blaster driver if necessary.
• Execute the demo batch file “SoCKit _IR.bat” under the batch file folder, SoCKit _IR
\demo_batch.
• After Nios II program is downloaded and executed successfully, a prompt message will be
displayed in nios2-terminal.
• Point the IR receiver with the remote-controller and press any button
• the information will be displayed in nios2-terminal, shown in Figure 5-13.
Figure 5-13 Running results of the IR demonstration
Figure 5-14 illustrates the setup for this demonstration.
67
Figure 5-14 The Setup of the IR receiver demonstration
5
5
.
.
6
6
T
T
e
e
m
m
p
p
e
e
r
r
a
a
t
t
u
u
r
r
e
e
D
D
e
e
m
m
o
o
n
n
s
s
t
t
r
r
a
a
t
t
i
i
o
o
n
n
This demonstration illustrates how to use the ADT7301 device with the Nios II Processor to realize
the function of board temperature detection. Figure 5-15 shows the system block diagram of this
demonstration. The ambient temperature information, which is collected by a built-in temperature
sensor on the SoCKit board, can be converted into digital data by a 13-bit A/D converter. The
generated digital data will be stored into the Temperature Value Register.
The sensor connects the FPGA device through a SPI interface. In this demonstration, a SPI master
core is used by Nios II software to access the sensor’s Temperature Value registers. Based on the
register’s values reading out in every five seconds, the program calculates the centigrade degree.
The relative values are finally displayed onto the nios2-terminal window, in order to let the user
monitor the board real-time temperature.
68
Figure 5-15 Block diagram of the Temperature Demonstration
D
D
e
e
m
m
o
o
n
n
s
s
t
t
r
r
a
a
t
t
i
i
o
o
n
n
S
S
o
o
u
u
r
r
c
c
e
e
C
C
o
o
d
d
e
e
• Project directory: SoCKit_TEMP
• Bit stream used: S0Ckit_TEMP.sof
• Nios II Workspace: SoCKit_TEMP\Software
D
D
e
e
m
m
o
o
n
n
s
s
t
t
r
r
a
a
t
t
i
i
o
o
n
n
B
B
a
a
t
t
c
c
h
h
F
F
i
i
l
l
e
e
Demo Batch File Folder: SoCKit_TEMP\demo_batch
The demo batch file includes the following files:
• Batch File: SoCKit_TEMP.bat, SoCKit_TEMP_bashrc
• FPGA Configure File : SoCKit_TEMP.sof
• Nios II Program: SoCKit _TEMP.elf
D
D
e
e
m
m
o
o
n
n
s
s
t
t
r
r
a
a
t
t
i
i
o
o
n
n
S
S
e
e
t
t
u
u
p
p
,
,
F
F
i
i
l
l
e
e
L
L
o
o
c
c
a
a
t
t
i
i
o
o
n
n
s
s
,
,
a
a
n
n
d
d
I
I
n
n
s
s
t
t
r
r
u
u
c
c
t
t
i
i
o
o
n
n
s
s
• Make sure Quartus II and Nios II are installed on your PC.
• Power on the SoCKit board.
• Connect USB Blaster to the SoCKit board and install USB Blaster driver II if necessary.
69
• Execute the demo batch file “SoCKit _TEMP.bat” under the batch file folder, SoCKit _TEMP
\demo_batch.
• After Nios II program is downloaded and executed successfully, the related information will be
displayed in nios2-terminal , shown in Figure 5-16.
Figure 5-16 Running results of the Temperature demonstration
70
Chapter 6
Steps of Programming the
Quad Serial Configuration
Device
6
6
.
.
1
1
R
R
e
e
v
v
i
i
s
s
i
i
o
o
n
n
H
H
i
i
s
s
t
t
o
o
r
r
y
y
This chapter describes how to program the quad serial configuration device with Serial Flash Loader (SFL)
function via the JTAG interface. User can program quad serial configuration devices with a JTAG indirect
configuration (.jic) file. To generate JIC programming files with the Quartus II software, users need to generate a
user-specified SRAM object file (.sof), which is the input file first. Next, users need to convert the SOF to a JIC
file. To convert a SOF to a JIC file in Quartus II software, follow these steps:
Before you Begin
Usually Quartus II includes a Serial Flash Loader (SFL) function .sof file for every FPGA device. Users just have
to use Programmer to open an FPGA‘s .jic file, and Programmer will automatically include a supported .sof file
for the respective FPGA. Currently, however, there isn’t support for .sof files for the Cyclone V SOC FPGA in
Quartus II v13.0. Users can remedy this situation by copying the sfl_enhanced_01_02d020dd.sof file from the
Demonstration\SFL folder on the SoCKit System CD, to the programmer folder under your Quartus II installation
(i.e. C:\altera\13.0\quartus\common\devinfo\programmer).
In addition, to use the Quad s serial flash as an FPGA configuration device, the FPGA will need to be set in Asx4
mode. To do this, adjust the configuration mode switch (SW6) to let MSEL[4..0] to be set as “10010”.
71
Convert. SOF File to .JIC file
1. Choose Convert Programming Files on Quartus window (File menu).
Figure 6-1. File menu of Quartus
2. In the Convert Programming Files dialog box, scroll to the JTAG Indirect Configuration File (.jic) from
the Programming file type field.
3. In the Configuration device field, choose EPCQ256.
4. In the Mode field, choose Active Serial X4.
5. In the File name field, browse to the target directory and specify an output file name.
6. Highlight the SOF data in the Input files to convert section. See
Figure 6-2.
74
Figure 6-4. Select Devices Page
Figure 6-5. Convert Programming Files Page
Write JIC File into Quad Serial Configuration Device
To program the serial configuration device with the JIC file that you just created, add the file to the Quartus II
Programmer window and follow the steps:
1. When the SOF-to-JIC file conversion is complete, add the JIC file to the Quartus II Programmer window:
i. Choose Programmer (Tools menu). The Chain.cdf window displays.
ii. Click Add File. From the Select Programming File page, browse to the JIC file.
iii. Click Open.
2. Program the serial configuration device by checking the corresponding Program/Configure box, a Factory
default SFL image will be load (See
Figure 6-6).
75
Figure 6-6. Quartus II programmer window with one JIC file
3. Click Start to program serial configuration device.
Erase the Quad Serial Configuration Device
To erase the existed file in the serial configuration device, follow the steps listed below:
1. Choose Programmer (Tools menu). The Chain.cdf window displays.
2. Click Add File. From the Select Programming File page, browse to a JIC file.
3. Click Open.
4. Erase the serial configuration device by checking the corresponding Erase box, a Factory default SFL image
will be load (See Figure 6-7).
76
Figure 6-7 Erasing setting in Quartus II programmer window
5. Click Start to erase the serial configuration device.
77
Chapter 7
Appendix
7
7
.
.
1
1
R
R
e
e
v
v
i
i
s
s
i
i
o
o
n
n
H
H
i
i
s
s
t
t
o
o
r
r
y
y
Version
Change Log
V0.1
Initial Version (Preliminary)
V0.2
Add CH5 and CH6
V0.3
Modify CH3
7
7
.
.
2
2
C
C
o
o
p
p
y
y
r
r
i
i
g
g
h
h
t
t
S
S
t
t
a
a
t
t
e
e
m
m
e
e
n
n
t
t
Copyright © 2013 Terasic Technologies. All rights reserved.
